360 Assembly/360 Instructions/BCR

BCR — Branch on Condition Register — Opcode 07 / Decimal 7 — 2 byte RR Instruction.

Format

BCR mask_value,branch_register (both values are 0 to 15)

BCR 6,1

RR Instruction (2 bytes)
	Byte 1 bits (0-7)	Byte 2
		Mask value (8-11)	branch register (12-15)
(in hex)	Opcode 07	(4 bits) 0..F / (dec 0..15)	(4 bits) 0..F / (dec 0..15)

The first argument is a mask which the condition code is compared against.
The second argument is the source register whose contents are to be used as the location to transfer to if the mask matches the currently set condition code.
The Mask value and base register values are 0 to 15.

Availability

The BCR instruction is available on all models, 360, 370 and z/System.

Usage

This instruction provides three types of branch operations: no branch (equivalent to no operation), branch conditionally depending on a mask value, and unconditional branch.

 BCR   0,0  No branch

Note: Since it may be difficult to understand the difference between the mask and register values, to distinguish between the mask value and the register, registers will be referenced by using the label R followed by the register number, e.g. R5 for Register 5, R6 for Register 6, R14 for Register 14, etc.

 BCR   2,R5
 BHR   R6 - Special opcode: Branch if High Register, same as BCR 2,R6
 BCR   1,R1
 BOR   R1 - Same as BC 1,R1
 BCR   15,R10
 BR    R10  - BR opcode is unconditional branch
              and is same as BCR 15,R10
 BCR   3,R6

If the mask or base_register is zero, the instruction is a no-operation, and does not branch.
If the mask is 15 the branch is unconditional (unless the base_register is 0, in which case it does not branch). So in either of the following cases:

 BCR   X,0
 BCR   0,X

Where X is any value from 0 to 15, the branch is not taken.

Mask

After executing an instruction which does an arithmetic, test or comparison, the processor sets the "Condition Code" flags (bits 18 and 19) in the PSW register, allowing the condition code to be examined for a potential branch. For example, suppose we are using an arithmetic instruction e.g. arithmetic add called "AR". Then in following conditions the value of "Condition Code" will be as following:

Condition	Symbol	Condition code in PSW
Result is zero	Z	0
Result is negative	N	1
Result is positive	P	2
Result overflows	O	3

Then consider for example instruction "BNZR". It's mask is 7. What does that mean? This instruction branches if the result is not zero, which means it branches if the value of condition code is not zero. So it is 1,2 or 3. Consider the following table

Z	N	P	O
0	1	1	1

The example above gives us mask (0111) = 7. For each of following opcodes you can construct the table ZNPO and find the corresponding mask.

Other Opcodes

The assembler provides the mask as part of several optional opcodes. These opcodes simply require the base register, which contains the target address to which to branch. The opcodes are as follows:

Opcode	Mask	Usage	Purpose	Equivalent to	Used after
NOPR	0	`NOPR R6`	No Operation	`BCR 0,R6`	Any place where a no-operation/filler is wanted. The value contained in the register is ignored.
BOR	1	`BOR R6`	Branch on Overflow/Ones	`BCR 1,R6`	After an arithmetic operation or arithmetic comparison, if arithmetic overflow or result is all ones occurred
BHR	2	`BHR R6`	Branch (a High)	`BCR 2,R6`	After any comparison, branch if first value in comparison is higher than second value (A > B)
BPR	2	`BPR R6`	Branch on Plus	`BC 2,R6`	After an arithmetic operation or arithmetic comparison, branch if result is positive
BLR	4	`BLR R6`	Branch (a Low)	`BCR 4,R6`	After any comparison, branch if first value is lower than second (A < B)
BMR	4	`BMR R6`	Branch on Minus/Mixed	`BCR 4,R6`	After an arithmetic operation or arithmetic comparison, branch if the result is negative or is ones and zeroes
BNER	7	`BNER R6`	Branch Not Equal	`BCR 7,R6`	After any comparison, branch if first value is not equal to the second value (A <> B or A ~= B or A != B)
BNZR	7	`BNZR R6`	Branch Not Zero	`BCR 7,R6`	After an arithmetic operation or arithmetic comparison, branch if result is not zero
BER	8	`BER R6`	Branch (a Equal b)	`BCR 8,R6`	After any comparison, branch if first value equals the second value (A = B or A == B)
BZR	8	`BZR R6`	Branch on Zero	`BCR 8,R6`	After an arithmetic operation or arithmetic comparison, branch if result is zero
BNLR	11	`BNLR R6`	Branch (a Not Low)	`BCR 11,R6`	After any comparison, branch if first value is not lower than the second value (A >= B)
BNMR	11	`BNMR R6`	Branch Not Minus	`BCR 11,R6`	After an arithmetic operation or arithmetic comparison, branch if result is zero
BNHR	13	`BNHR R6`	Branch Not High	`BCR 13,R6`	After any comparison, branch if first value is not higher than the second value {A<=B)
BNPR	13	`BNPR R6`	Branch Not Plus	`BCR 13,R6`	After an arithmetic operation or arithmetic comparison, branch if result is not positive
BNOR	14	`BNOR R6`	Branch Not Ones	`BCR 14,R6`	After an arithmetic operation or arithmetic comparison, branch if result is not all ones
BR	15	`BR R6`	Branch (unconditional)	`BCR 15,R6`	Branch in all cases (unless index register is 0; then treat as no-op) Equivalent to GOTO in high-level languages

Optional formats

Mask value ignored

07FE            BR    14     unconditional branch -  equivalent to BCR 15,14
0705            NOP   5      no-operation - BCR 0,5
07F0            BCR   15,0   despite the mask being 15, because the base register is 0,
         *                   this is also a no-op

Used after standard comparison of a and b

0785            BER   5      branch if a equal b - BCR 8,5
0725            BHR   5      branch if a high - BCR 2,5
0745            BLR   5      branch if a low - BCR 4,5
0775            BNER  5      branch if a not equal b - BCR 7,5
07D5            BNHR  5      branch if a not high - BCR 13,5
0745            BNLR  5      branch if a not low - BCR 4,5

Used after arithmetic operations

0715            BOR   5      branch on overflow - BCR 1,label
0727            BPR   7      branch on plus - BCR 2,7
0745            BMR   5      branch on minus - BCR 4,5
0785            BZR   5      branch on zero - BCR 8,5
07E5            BNOR  5      branch on not ones - BCR 14,5
07D5            BNPR  5      branch on not plus - BCR 13,5
07B5            BNMR  5      branch on not minus - BCR 11,5
0775            BNZR  5      branch on not zero - BCR 7,5

Used after Test Under Mask instructions

4717            BOR   7      branch on ones - BCR 1,7
474F            BMR   15     branch on mixed - BCR 4,15
478E            BZ    14     branch on zeroes - BCR 8,14
47E5            BNO   5      branch on not ones - BCR 14,5

Availability

The BCR instruction is available on all models of the 360, 370 and z/System.

Operation

Upon performing an arithmetic operation or a comparison, certain bits in the Program Status Word called the Condition Code are set or cleared. In the case of comparison of two fields, the left value is considered the "A" value, and the right value is considered the "B" value, and the result of the comparison of A to B tests how A compares to B, either low, high, equal or not-equal.

In the case of an arithmetic operation, the result being plus, minus, zero or having had an overflow is tested.

In the case of the test under mask instructions, the result of the test being all ones, all zeroes, or mixed ones and zeroes.

The unconditional branch (BCR 15,base_register) is the equivalent of a return statement or other exit from a procedure or function to the calling procedure or program in a high-level language.

The Branch on Condition Register instruction is used following such a test to compare the condition code bits to the mask value. If bits set in the mask match bits which are set in the condition code (or all of the bits in the mask are set), and the base register of the target address is not 0, the target address contained in the base register is placed into the PSW as the new address of the current instruction and the branch is taken. Otherwise execution continues with the next instruction following the branch on condition register instruction.

Typically, the Branch on Condition Register instruction is most often used in module to module transfers or branch from one CSECT to another. In the case of a conditional branch being used within the same module or CSECT, the Branch on Condition (BC) instruction (or the optional formats, BE, BNE etc.) is more often used.

Purpose of Instruction

The Branch on Condition Register instruction is used to branch within a program. It has three variations: no branch or No Operation, conditional branch depending upon a test, or unconditional branch.

No Operation

The no branch - BCR 0 - or NOPR is typically used to create a label which is not tied to an existing instruction. It may be used by a macro for alignment to force an instruction or data onto a specific boundary but without causing a program exception if the instruction is branched to. It can also be used to provide 'slack' space to allow later patching of the binary without having to reassemble the program. A NOPR will also occur, regardless of the mask value, if the base register of the branch is zero.

Conditional Branch

In a conditional branch the bits in the mask are compared to the bits in the condition code. If the bits in the mask match the bits in the condition code, (and the base register of the target address is not zero) the branch is taken.

Unconditional Branch

A branch to another location (the equivalent of a GOTO in high-level languages or a RETURN if inside of a procedure or subroutine) is performed by setting all the bits in the mask, e.g. BCR 15, or using the BR instruction. As long as the base register is not zero, the branch will always be taken; if the base register is zero, the branch is never taken.

Typical Usage

The branch on condition register and optional formats are typically used after performing a comparison or arithmetic operation. In the following code, a question is asked, the response is compared to yes or no, and the question is re-issued if not either. The 'CALL' macro is used to create a standard subroutine linkage. In this example, a no response is handled internally (at label NO) while a yes response transfers control to another routine (called YES)

CHECKINQ NOP  0(0)  
* Optionally, the instruction 'CHECKINQ EQU *' could have been used. This would have
* generated no instructions.           
         BALR 3,0                             Come back here if neither Y nor N
* optionally, the instruction LA 3,CHECKINQ  could have been used.    :
         USING *,3                             Let Assembler ue R3 for local addresses
         L    4,YESRTN                         Place to go for Yes response
         LA   5,NO                             Place to go for No response
         CALL INQUIRE,(QUES,1,RESP)            Call an external module called INQUIRE 
         CLC  RESP(1),QY1                      Compare one byte for 'Y'
         BER  4                                "Resp" is the A value in an A:B comparison 
         CLC  RESP(1),QY2                      Now test (length 1) for 'y'
         BER  4 
         CLC  RESP(L'QN1),QN1                  Test 'N' (L' tells the assembler to use
*                                              the specied length of the named label)
         BER  5                                Answer was 'N'
         CLC  RESP(1),QN2                      Is it 'n'?
         BNER 3                                Something else, try again
         BR   5                                Answer was 'n'
QUES     DC   C'Are you ready to start?'       Construct a 'C' language-type
         DC   X'00'                            string, zero terminated
RESP     DS   C                                One byte response
QY1      DC   C'Y'                             Available responses
QY2      DC   C'y'
QN1      DC   C'N'
QN2      DC   C'n'
YESRTN   DC   V(YES)                           External module YES
*
* This will handle a 'no' answer
==Typical Usage==

The branch on condition register and optional formats are typically used after performing a comparison or arithmetic operation. In the following code, a question is asked, the response is compared to yes or no, and the question is re-issued if not either. The 'CALL' macro is used to create a standard subroutine linkage. In this example, a no response is handled internally (at label NO) while a yes response transfers control to another routine (called YES)

CHECKINQ NOP  0(0)  
* Optionally, the instruction 'CHECKINQ EQU *' could have been used. This would have
* generated no instructions.           
         BALR 3,0                             Come back here if neither Y nor N
* optionally, the instruction LA 3,CHECKINQ  could have been used.    :
         USING *,3                             Let Assembler ue R3 for local addresses
         L    4,YESRTN                         Place to go for Yes response
         LA   5,NO                             Place to go for No response
         CALL INQUIRE,(QUES,1,RESP)            Call an external module called INQUIRE 
         CLC  RESP(1),QY1                      Compare one byte for 'Y'
         BER  4                                "Resp" is the A value in an A:B comparison 
         CLC  RESP(1),QY2                      Now test (length 1) for 'y'
         BER  4 
         CLC  RESP(L'QN1),QN1                  Test 'N' (L' tells the assembler to use
*                                              the specied length of
         BER  5                                Answer was 'N'
         CLC  RESP(1),QN2                      Is it 'n'?
         BNER 3                                Something else, try again
         BR   5                                Answer was 'n'
QUES     DC   C'Are you ready to start?'       Construct a 'C' language-type
         DC   X'00'                            string, zero terminated
RESP     DS   C                                One byte response
QY1      DC   C'Y'                             Available responses
QY2      DC   C'y'
QN1      DC   C'N'
QN2      DC   C'n'
YESRTN   DC   V(YES)                           External module YES
*
* This will handle a 'no' answer
         DROP 3                                Tell assembler Reg. 3 is no
*                                              longer available for addressing                                     
NO       NOP  0(0)                             Handle a no

Exceptions and Faults

The target address contained within the base register must not be odd, or an operation exception occurs
The target address contained within the base register must be within the range of valid memory or an operation exception occurs.
The storage key for the target address contained within the base register must be the same as the current process (or this process must have a key of 0) or a memory protect violate exception occurs.

Alternative branch instructions

The BALR instruction is used to branch to the address in a register and save the current address as a return address, similar to a procedure or function call in a high-level language
The BC instruction is used in the same manner as the BCR instruction, but is used to branch to the address contained in a register plus a potential index register and a 12-bit displacement as opposed to the address contained in a register.
The BCT and the BCTR instructions are used to decrement the value in the first argument, a register, store the result back in that register, then branch to an address in a register (for the BCTR instruction) or to the address contained in a register plus a potential index register and a 12-bit displacement, if the resulting value in the first argument register was not zero.
The BRC instruction is used in the same manner as the BCR instruction, but is used to branch to the address relative to the current program counter, contained in an immediate (16 bit) value.
The BRCL instruction is used in the same manner as the BCR instruction, but is used to branch to the address relative to the current program counter, contained in an immediate (32 bit) value.

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