360 Assembly/360 Instructions/ALR

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ALR - Add Logical Register - Opcode 1E



ALR 2,1

The specific syntax is

ALR target register, source register.
RR Instruction (2 bytes)
Byte 1 Byte 2
target register source register
(8 bits)
(4 bits)

(4 bits)

  • The first argument is a target register which value is affected by the instruction.
  • The second argument is the source value register.


The ALR instruction is available on all models of the 360, 370 and z/System.


The ALR instruction reads 32-bit integer value from the register specified by the second argument and adds it to the value of the register specified by the first argument. The least significant 32 bits of the 33-bit result sum is placed to the target register. The Condition Code field in the Program Status Word is changed according to the resulting value (sum), treated as unsigned integer (see below).

As this is a 32-bit instruction, on the zSystem, the high 32 bits of the register are unaffected.

Condition CodesEdit

The least significant bit of CC field of the PSW is set if sum is not zero and cleared otherwise. The most significant bit of CC field of the PSW keeps carry bit (i.e. the most significant bit of the 33-bit sum).

Exceptions and FaultsEdit



The AL and ALR instructions are useful to implement adding of integer values longer than 32 bit. In that case, one should use AL or ALR to count all parts of the sum (possibly except the most significant one), and, if CC is 2 or 3 after the adding (i.e. carry have happened), increment the nearest higher part of the sum.

Related instructionsEdit

16 bitEdit

  • To add half-word see AH
  • To subtract haLF-word, see SH


  • To add logical word value from memory, see AL.
  • To add signed value from memory, see A
  • To add signed value from register, see AR
  • To subtract logical value, see SL or SLR.
  • To subtract signed value, see SR, S,

Floating PointEdit

  • To add floating-point values, see AE, AER, AD or ADR.

Condition CodeEdit

  • To check condition code, see BC or BCR.
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