VHDL for FPGA Design/Priority Encoder

< VHDL for FPGA Design

Priority EncoderEdit

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY encoder74 IS							
	PORT 	(clk,res,sin :IN STD_LOGIC;	
			outpt :OUT STD_LOGIC);		
END encoder74 ;							

ARCHITECTURE struc OF encoder74 IS 
			SIGNAL txlss : STD_LOGIC_VECTOR(3 downto 1);

BEGIN
PROCESS
BEGIN

WAIT UNTIL FALLING_EDGE (clk);
		IF (res = '1') THEN			
			txlss <= "000";
		ELSIF (res = '0') THEN
			txlss(1) <= inpt;
			txlss(2) <= txlss(1);
			txlss(3) <= txlss(2);
			outpt<= (sin XOR txlss(2) XOR txlss(3));
END IF;
END PROCESS;
END struc;

Simulation WaveformEdit

  

Generated Logic CircuitEdit