If a logic gate with a different number of inputs to the one available is required, one can be built up from the gates that are available. This is done by cascading the gates. Gates which are the "basic" gates (i.e. AND, OR, XOR) can be directly cascaded. The "negated gates" (NAND, NOR, XNOR) can't, and these are made up of the counterpart basic gate with an inverted output.
AND Gates and General NotesEdit
An AND gate will only give a high output if ALL inputs are also high. In the diagram depicting a three-input gate below, if either or both of inputs 1 or 2 goes low, the first AND gate will give a low, disabling the second AND gate. If input 3 goes low, the second gate is disable, regardless of the state of inputs 1 and 2.
To make gates with higher numbers of inputs, just add gates on to the "end" of the cascade, as shown for a 5-input example below.
If the circuit is going to be used at high frequencies, the fact that if input 1 changes the propagation time will be five times that of one gate, it might be better to use the following layout, where the propagation time will be only 3 times that of one gate. For normal applications this should not be a problem, as the propagation times for a CMOS gate at 5V is typically about 50 nanoseconds (one twentieth of a millionth of a second).
Both this layout and the standard cascade use exactly the same number of gates: for an n-input gate, n-1 2-input gates are needed. This is also true for OR and XOR gates, which also can be laid out as above for shorter propagation times. For the next sections the slightly simpler basic cascade will be used for clarity.
If a lot of inputs are going to be needed, consider using a 3-, 4- or 8-input AND gate to start with, as the laout of the circuit will be much easier, and less ICs will be needed (one 4081 Quad 2-Input AND Gate IC can make a 5-input AND gate, whereas one 4068 8-Input AND Gate IC provides three more inputs in the same size IC package, with less wiring to be done). The same goes for other gates.
NAND gates cannot be successfully cascaded to make a larger NAND gate, as having one of inputs 1 or 2 and input 3 high will give a low (two high inputs at the second gate), when really it should be a high.
It is possible to make an n-input NAND gate from 2-Input gates, but an extra inverter (or NAND gate with joined inputs as below - this means only NAND gates are required) is required after every NAND gate that "coallates" two inputs or signals, but not after the final gate:
NAND gates can also be made by using cascaded AND gates with an inverter at the end:
The disadvantage of this is that it requires two different type of gate (AND and NOT, which require two different ICs), but has the distinct advantage that significantly fewer gates are needed (in the inverted version n-2 inverters are required). This becomes a factor in larger cascades.