Referring to Professors Niklaus Wirth and Jurg Gutknecht, Project Oberon, The Design of an Operating System, a Compiler, and a Computer, ISBN 0-201-54428-8, Revised Edition 2013.


Compilation of a module produces branches in which target addresses are relative to the base of the module. Fixup is the conversion of these addresses to absolute addresses. The necessity of fixup in module loading is discussed in section 6.1. Linking and loading, page 79.

In section "6.3. The linking loader" is the paragraph beginning "At the very end of the file three integers called fixorgP, fixorgD, and fixorgT are read."

a) A search for "fixorgP" in the code generator module ORG will find this line in ORG.Call.

Put3(BL, 7, ((-x.r) * 100H + x.a) * 1000H + pc-fixorgP); fixorgP := pc-1

Also, this line is in ORG.Put3.

code[pc] := ((op+12) * 10H + cond) * 1000000H + (off MOD 1000000H); INC(pc)

b) -x.r in an item x for a procedure is the module number, mno, and x.a is the entry number for the procedure, pno.

c) From ORG.Call and ORG.Put3 deduce,

the 4 bits [20..23]  = -x.r (= the module number, mno)
the 8 bits [12..19]  =  x.a (= the entry number for the procedure, pno) 
the 12 bits [0..11]  =  pc-fixorgP (= the displacement between 2 instructions in the fixup chain)

d) These lines correspond to the following lines in Modules.Load.

mno := inst DIV 100000H MOD 10H;
pno := inst DIV 1000H MOD 100H;
disp := inst MOD 1000H;

The compiler generates the instruction | BL (4) | cond (4) | mno (4) | pno (8) | pc-fixorgP (12) |, which the module loader then fixes up to | BL (4) | cond (4) | offset relative to PC (24) | .

Refer to ORG.Call and Modules.Load and mailing list at 2019-11-18.

Sources in Oberon V5Edit

Published V5 Variant Notes
  Out.Mod Allow delay of execution of Append, using a flag variable.
  Out1.Mod Allow delay of execution of Append, using a procedure variable.