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MyHDL and the NEXYS 2 Board/Things we can safely ignore

For purposes of this book we'll ignore a few things.

Modern FPGAs are designed to minimize clock skew. In a system with a large number of edge-sensitive flip-flops all watching the same clock, you might imagine that if the clock had to travel some distance, that edge would arrive at different flip-flops at different times. In the worst case, that time difference might mean that a D-input failed to satisfy the setup and hold times relative to the clock edge for one or more flip-flops, and as a result, the circuit's behavior was unpredictable. This is a concern for logic circuits spanning several boards with several chips on each board. But within a single FPGA, clock skew can safely be ignored because FPGA manufacturers are careful to provide clock distribution circuitry that keeps all the edges in close alignment.

Fan-out...

Parasitic effects...

Transmission line effects...

Asynchronous logic...