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Clock and Data Recovery/Introduction

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Timing in serial data transmissionEdit

To transmit digital information over a certain distance, it is necessary to serialise it (just one guiding medium like cable, fiber,etc. but very high bit rates).

The digital information is often encoded for error detection and correction.

The bit stream is transmitted with its clock information.

The resulting signal, during its journey, is affected by noise and by the transfer function of the transmission medium, and undesired corruption of the information content may follow.

At the receiving end, the signal is restored (it is equalised and the noise filtered out) as much as possible.

Then the timing information is extracted, and the bit stream regenerated.

The electronic circuits that accomplish these last functions inside the data receiver are called the Clock and Data Recovery block (= the CDR).

The timing information, i.e. the clock, is essentially carried by the level transitions of the received signal.

The action of recuperating the clock signal from the received signal is inevitably affected by some deterioration: the square wave extracted is not exactly synchronous with the transmit clock.

Data and clock, during their travel together, have been affected by the noise and by the inter-symbol interference and have acquired:

  • some inevitable delay, due to the physical transit time, and to the extraction process,
  • some timing inaccuracy (= phase modulation, called jitter)
  • some errored bits with a (very) low probability, or –in other words- a bit error rate of very low value (e.g. < 10−19)

The jitter can be kept to a minimum with sophisticated clock extraction circuits, but not eliminated.

On the other hand, in the network topology there are always points where signals that had been originated by the same clock and have cumulated different jitters along different transmission paths, must be put together again.

To absorb the jitter differences an elastic buffer (a special type of buffer memory) is used.

Serial vs parallelEdit

Information is stored in a memory, in the forms of bits written inside the cells of the memory.
Most memories are made by groups of cells (memory words) with a unique address, that accomodate 8 or 16 bits of information each.
The content of a part of a memory partition must be " transmitted " to make its information content available elsewhere. " Transmitted " means sent electronically and replicated inside a similar part of another memory.
As each memory stores and outputs its content via a bus as wide as each of its words, the bits of a word can be transmitted all at the same time on a bus of links, with as many links as the memory bus is wide (often with one more link to transmit the clock that times the bits of each subsequent word).
This is called a parallel transmission. The clock that times the transmission of each word content has a frequency equal to:
(bits transmitted each second) / (number of bits in a word) [Hz].
A parallel transmission becomes unpractical when the bit rate on the links exceeds a certain limit.
The (parallel) links carry the information bits as electromagnetic signals (electric or optical).
The parallel links are never of the same physical length, length that can be measured as how many bit clock periods the information bits take to travel through them.
A single clock at the end of the links may be unable to load all the bits of a given word together into the receiving memory, if they have suffered largely different delays during the transmission.
The delay difference amongst different parallel paths causes bits, that have been sent at the same instant on different paths, to be received in different clock cycles of the clock at the receiving end. Unless additional (and complex) tricks are used, the parallel transmission is impossible at that distance.
(The distance difference is inclusive of different delays in the electronic circuitry of each path, transmit and receive).
The parallel transmission is limited by the length difference of the parallel paths.
To put the shifted streams of bits back in sync, it is necessary to insert redundant bits inside each path at the transmit stage, so that a frame sync can be detected at the receive end. Then buffer memories at the end of each path will be used to put back in sync all the bits of the parallel paths. Interfaces with this structure have been proposed, and are in use in some systems.
In most practical applications though, the approach of serialising several parallel streams of bits (typically 8 or 16),i.e. a serial transmission with the multiplication of the clock frequency, has been found preferable to the alternative approach of adding the sync structure on each bit stream at the transmit end and to recover the correct parallelism, with use of buffer memories, at the receiving end.
Parallel transmission is practical when different paths have delay differences shorter than a quarter of a bit interval, and cost effective when the connections to the bus of links are not expensive .

A serialised transmission, with clock and data encoded together on a single link, becomes necessary when different links travelled by parallel streams differ by 25% or more of a bit period at their bit rate. It should be emphasised that the serial transmission needs a multiplexing of the n bits of each word before transmission, and demultiplexing at the end, to present in parallel the bits of every word. The serial transmission takes place at a bit rate n times higher than the corresponding parallel transmission. The serial transmission can reach distances independent from the accuracy of defining the link length, and are always preferred for all types of transmission media when the distance is longer than a few meters. Often serial transmission of inherently word structured data (~ byte structured data) is used even for shorter distances. The serial transmission is only limited by the total length a transmission technique can reach. Using optical fiber this means orders of magnitude more.

For example: at 1 Gbps the wavelength to refer to is:

c/(1 GHz) = 3 * 108 m/s / 109 sec-1 = 30 cm.

Considering that on PCB the speed is 40% lower than in vacuum, the reference distance is 60% of 30 cm, or about 20 cm. As a result, serial encoded transmission (at n-times 1 Gbps, e.g. 8 Gbps if the parallel links are 8) becomes preferred when distance differences amongst the parallel paths (used at 1 Gbps) are 5 cm or more. If copper of fiber cables are considered (equipment local or long interconnections), the choice of serial becomes more advantageous, because of the larger cost of the parallel cables and connectors.

CDRs and PLLsEdit

This book deals with CDR (Clock and Data Recovery) circuits, but just the PLLs (Phase Locked Loops) that they incorporate are the circuit blocks that are analyzed and studied.

These PLLs are the important part of a CDR (= used for the Clock Recovery, = the CR part of the CDR).

The DR (Data Recovery) part of the CDR is not studied in any depth, and only the PLLs that are fit for the Clock Recovery function are studied here.

PLLs used for other applications, like for instance position detection of mobile objects or identifications of non-modulated signals, are not considered.

In recent years, owing to the explosive growth of mobile phones, a lot of development has been made on PLLs inside frequency synthesizers (they are not CDRs). It may be said that nowadays a very large part of the PLLs implementations are in frequency synthesizers.

What is special in PLLs for CDRs is a direct consequence of the "blending" of information bits with their clock into a unique serial stream of pulses. Often a NRZ transmission of the information bits does the job perfectly. For other transmission channels a different "encoding" of bits and clock may optimise better the overall performances and increase the distance beyond which a regeneration is needed.

In all cases the "blended" serial stream, owing to the essential "impredictability" of the information bits, does not have a spectrum with neat lines at fixed frequencies but is spread out with large lobes; its level transitions do not occur at each of the possible instants but randomly on just part of them. The concept of "transition density" is used in this book to simplify the mathematics. Moreover, these transitions, when they occur, jitter with respect to their ideal positions because of channel distortion and noise.

On the contrary, the signal that a frequency synthesiser locks into, is a regular periodic waveform, with a spectrum close to a strong line with noise sidebands. Its level transitions occur with a 100% density.

What this book is all about (i.e. application-structure correspondence)Edit

This book intends to provide a good theoretical base for the understanding, the study and the engineering of PLL systems meant for CDR applications.

The PLL of a CDR is a unity feedback system because the output (the recovered clock) should be as close as possible to the input (the clock embedded in the incoming pulse stream), apart from the rejection of high frequency components of the latter.

CDRs that are made up entirely of circuit blocks that behave linearly are well described by the linear mathematical models, i.e. by linear differential equations with time as independent variable and by their Laplace or Fourier transforms.

Any PLL of a CDR can be described by one out of three "control loop structures" (= architectures, in the sense of block diagrams).

They can be identified just by the two numbers of their order and their type. The figure here below identifies the three architectures from their linear models.

The structures implemented in practice with all linear blocks are:

  1. Loops of 1st order and of type 1, for applications of "phase aligners" and of "end points".
  2. Loops of 2nd order and of type 1, for applications of "regenerators"

CDRs with one or more hard non-linearities can not be sufficiently described by linear mathematical models. ( Additional simulations recomputed for each different signal level are needed).

The widespread (and often inevitable) use of essentially non-linear phase comparators (bang-bang) leads to the use of the more tolerant and robust architectures. (The gain of the bang-bang phase detector is not fixed, but varies with the phase difference at its inputs).

Such structures can still be identified by the numbers of order and type of the corresponding linear loops,

and are in practice:

  1. Loops of 1st order and of type 1 (exactly as in 1.1.), for applications of "phase aligners" and of "end points".
  2. Loops of 2nd order and of type 2 (if a linear phase comparator is used this structure is non-preferred) for applications of "regenerators" and of "end points". A detailed analysis of a linear (2.2) architecture (with all linear blocks) is still very important for the comprehension of its practical applications with a bang-bang phase detector.

In the book, for all the listed cases (1.1., 1.2. and 2.2.):

  1. the linear model (functions of the complex variable   or of  , and of the real variable  ) is provided, so that the operation in "small signal" conditions can be studied (jitter tolerance, jitter transfer, noise transfer, unit step response, etc.)
    1. of each PLL block and
    2. of the overall system
  2. Important points, where the linear model applicability is exceeded, are investigated, using results obtained trough numerical simulation.
Several versions of simulation programs have been developed and can be provided on request [1] .


  1. Requests can be mailed to: . The simulation programs accept as inputs the loop parameters and the input signal characteristics and provide as output a representation of the "large signal" behavior in those conditions, e.g. of the loop acquisition waveform