Clock and Data Recovery/Buffer Memory (Elastic Buffer)< Clock and Data Recovery
Data Buffers in association with CDRsEdit
The CDR function is primarily a layer 1 function, in the sense of the OSI Reference Model.
In the scope of CDR applications, the Telecom buffer further specializes to simply add a convenient delay to a serial data stream.
Such buffer, in principle, consists of a R/W memory with circularly sequential addresses, and of two counters.
The write counter times the writing into the memory of an incoming serial flow of information, and the read counter sets, in turn, the timing of the reading operation.
In general a buffer memory may be used to absorb delays, or just delay variations (wander and/or jitter), generated by transmission over physical media, or by software elaboration, or other types of delays.
If the buffer is meant to absorb delay variations due to the transit along a transmission path (that is: designed to absorb wander and/or jitter),
then its size in bytes (or in bits) is smaller,
the control of the phase relation between the write and the read clocks is more accurate,
and its name specializes into “elastic buffer”.
An adder compares the content of the two counters, computing the difference between the two.
Its output gives an indication of the relative phase of the two clock signals, very similar to the output of a phase comparator of a PLL:
- at the start-up of the system, the write counter is set to 0, and the reading counter is set to half the memory depth.
- If the initial value of the read counter is set to less than half the memory depth, then less than the entire memory may be used and the transit delay through the elastic buffer may be less.
- When the buffer depth is small ( a few bits or a few bytes ), the elastic buffer can be just a shift register that:
- - is written (with the write clock) into the first flip-flop ;
- - is read (with the read clock) from the flip-flop along the register that corresponds to the delay (in number of cycles) from the read to the write clock.
The operation in time of an elastic buffer is sketched in the figure below:
The delay (=phase) of the transitions in the incoming pulse stream is jittered with respect to then average transmission delay.
The buffer adds a complementary delay so that the sum of the jitter delay plus the buffer delay are a constant amount at any time.
The buffer depth (= the register length) is equal to the maximum peak-to-peak jitter expected (plus some margin).
The delay added by the elastic buffer, in the time diagram, is a curve mirroring vertically the jitter (=delay) of the transitions of the incoming pulse stream.
The mirror is located at a delay equal to the average transit delay (plus some little margin).
A special case of elastic buffer is the "phase aligner"
- The phase aligner is an elastic buffer used inside a single clock domain. The CDR that recovers the write clock is typically implemented as a 1st order PLL.
- A more formal definition, without mention of the operation within a single clock domain, can be:
- The phase aligner is a buffer memory that shifts the phase of the received signal so that it matches the phase of a reference clock.
- in some application the phase aligner may be be defined as incorporating the CDR that recovers the write clock (wider definition), or not (stricter sense definition), as will be seen in the next page.
- In some specialized cases it may be defined as accomplishing a CDR function itself in cascade to the CDR that recovers the write clock (de-jitterizer)