Signetics 2650 & 2636 programming/Tutorial code - sync to VRST
Tutorial code - Sync to VRST edit
This is the code for the tutorial Sync to VRST
This code block must be merged with the standard 'Hardware definitions' code before it can be assembled |
; Tutorial SyncVRST
;=============================================================================
org 0
reset_vector: ; the microprocessor starts here when the reset button is pressed
bcta,un reset
org 3
interrupt_vector: ; interrupts shouldn't happen, but we set this just in case
retc,un
reset:
lodi,r0 $20 ; initialise program status word, just to be sure!
lpsu ; inhibit interrupts, stack pointer=0
lpsl ; register bank 0, without carry, arithmetic compare
eorz r0
stra,r0 effects ;initialise the 74LS378
stra,r0 objectsize ;all objects size 0
bsta,un DefineObjects ;define all objects
lodi,r0 $AA
stra,r0 score12
stra,r0 score34
eorz r0
stra,r0 effects ; !invert = 0
lodi,r0 0 ; X / 000 / 0 / 000
stra,r0 backgnd ; / black background / disabled / yellow screen
lodi,r0 %00011101 ; XX / 011 / 101
stra,r0 colours12 ; / obj1 red / obj2 green
lodi,r0 %00110000 ; XX / 110 / 000
stra,r0 colours34 ; / obj 3 blue / 4 white
endless:
bsta,un Vsync0 ; make sure VRST hasn't started
bsta,un Vsync1 ; wait for VRST to start
loda,r0 vc1 ; increment vertical position of object 1
addi,r0 1
stra,r0 vc1
loda,r0 hc1 ; decrement horizontal position of object 1
subi,r0 1
stra,r0 hc1
bctr,un endless
;===================================================================
; subroutine - define shapes and position of all objects
DefineObjects:
lodi,r3 $0E
lodi,r0 $FF
loopDS:
stra,r0 shape1,r3- ; create rectangular shapes
stra,r0 shape2,r3
stra,r0 shape3,r3
stra,r0 shape4,r3
brnr,r3 loopDS
retc,un
;=================================================================
; subroutine - wait for VRST to clear
Vsync0:
tpsu sense
bctr,eq Vsync0 ; wait for Sense bit to clear
retc,un
;=================================================================
; subroutine - wait for VRST to set
Vsync1:
tpsu sense ; wait for Sense bit to be set
bctr,lt Vsync1
retc,un
;=================================================================