Signetics 2650 & 2636 programming/2636 PVI
|This section of the book is primarily reference material for the PVI. More detailed discussions can be found in the Tutorials.|
The Signetics 2636 Programmable Video Interface (PVI) is a 40-pin DIL chip that handles a number of functions within the console:
- Video generation
- Screen colour
- Background grid
- Score digits
- Four objects (sprites)
- Object completion and collision detection
- Square wave audio
- A/D conversion for the analogue joysticks
- Chip select signals for memory and input/output devices
- 37 bytes of scratch memory
These functions are all implemented by reading and writing to various registers within the PVI.
Score digits Objects Background grid Object duplicates
Internally the PVI registers are located at addresses $F00 to $FFF. Within the console's memory map they are located at addresses $1F00 to $1FFF. Programmers only need to be concerned with these latter addresses, so those will be the ones we use throughout this book. For the same reason we will also ignore the areas where the memory map is duplicated.
Note that some control registers are write-only. If a program needs to know the contents of any of them, a duplicate copy must be saved elsewhere. Tests on some of these registers on one console indicate that if a read operation is attempted the contents will be corrupted.
|1FC0||Size object 4||Size object 3||Size object 2||Size object 1||Write only||Sizes of objects|
|1FC1||R1||G1||B1||R2||G2||B2||Write only||Colours of objects|
|1FC3||Format||Position||Write only||Score format and position|
|Write only||Grid enable and colours|
|1FC7||Sound||Write only||Tone period|
|1FC8||Score digit 1||Score digit 2||Write only||Values of the four score digits|
|1FC9||Score digit 3||Score digit 4|
|Read only||Collision status. Object display completion. VRLE set at leading edge of VRST. All bits reset when read or at trailing edge of VRST.|
|1FCC||A/D pot 1||Read only||A/D value, valid during VRST only.|
|1FCD||A/D pot 2|
The PVI has four, programmable, two-dimensional objects that can be positioned anywhere on screen in a single 3-bit colour in one of four different sizes. It is said that the PVI was the first device to have this capability. This style of graphic was later termed a sprite, but we will stick with 'object' in this book as it is the term used in the Signetics datasheet.
The shape of the object is set in a ten-byte array. Bits set to zero are transparent, while bits set to a one are displayed as the selected colour.
Object colours are set by registers $1FC1 and $1FC2. See Programming colours for details.
Objects can be displayed in four different sizes as set by two-bits in register $1FCO.
|x1||8 x 10||0||0|
|x2||16 x 20||0||1|
|x4||32 x 40||1||0|
|x8||64 x 80||1||1|
Positioning of objects is determined by reference to the origin of the tv scan at the top-left of the screen.
The horizontal coordinate (i.e. $1F0A) is set as the number of horizontal clocks to skip after the start of the raster line before the object is displayed. It maybe changed while the object is being displayed in which case the remainder of the object will be displaced. The vertical coordinate (i.e. $1F0C) of an object is set with an eight-bit unsigned value equal to the number of lines to skip before the object is displayed. This value must be set before the trailing edge of VRST.
One or more duplicate objects can be displayed further down the screen. The horizontal coordinate of the duplicate (i.e. $1F0B) is set in the same way as the original object. The vertical coordinate of the duplicate is set as the "number of lines to skip - 1" after displaying the last line of its predecessor.
The horizontal coordinate of the duplicate is read by the PVI on each line during HRST, so if it is changed during display of a duplicate, the rest of the duplicate will appear at a different position. The vertical coordinate of the duplicate must be programmed before the object completion status bit is set by the previous occurrence of that object.
When the last line of an object has been displayed an object complete bit is set in register $1FCA and the PVI generates an interrupt signal for the microprocessor.
If an object overlaps the background grid an object/grid collision bit is set in register $1FCA. If two objects overlap an inter-object collision bit is set in register $1FCB.
The four score digits may be displayed as either two separate 2-digit numbers or as a single 4-digit number. They may be displayed at the top or bottom of the screen, or by reprogramming during the vertical scan between lines 40 and 199 they may appear at both top and bottom. The mode of display is determined by the format and position bits of register $1FC3.
Each score digit is 12 clocks wide and 20 lines high.
The top position corresponds to lines 0 to 19 of the background grid, or vertical coordinates 20 to 39. The bottom position corresponds to lines 180 to 199, or vertical coordinates 200 to 219.
The colour of the score is the inverse of the colour programmed for the background grid. See: Programming colours
|Format = 0||28||44||76||92||12 34|
|Format = 1||28||44||60||76||1234|
The four score digits in $1FC8 and $1FC9 may be set to any hexadecimal value 0 to F. Values 0-9 display as the number, A-F display a blank.
The PVI has a programmable background grid comprised of an array of elements, 16 wide and 20 deep.
These elements are vertical bars, one pixel wide, arranged in pairs of horizontal rows; the first row of each pair is two raster lines deep and the second row is 18 raster lines deep. Each of these 320 vertical bars may be switched on or off by setting a bit in a 40-byte array located at memory addresses $1F80 - $1FA7.
The vertical bars may be extended horizontally, controlled by five registers $1FA8 - $1FAC. Each of the five extension registers control four consecutive rows of vertical bars.
Bits 5-0 of the extension register enable all of the vertical bars in a horizontal row to be extended to 8 pixels. The 18-line vertical bars are divided into two parts (A and B) each of 9 lines making it possible to extend the top and bottom part of the bars by 1, 2 or 4 pixels.
Bits 7-6 of the extension register enable all of the vertical bars in a group of four rows to be extended by to either 1, 2 or 4 pixels.
The colour of the background grid is set by bits 2-0 in register $1FC6. The background grid is enabled by setting bit 3 in register $1FC6. If the background grid is not enabled, registers $1F80-$1FAC maybe used as scratch memory, a whopping 45 bytes, in addition to the 37 bytes of scratch memory
The PVI can generate a single audio square wave output. Its frequency is set by register $1FC7. If this value is 0, the square wave is inhibited, otherwise its period is 2(n+1)TH, where n is the value set in $1FC7 and TH is the horizontal reset period. For a PAL system this simplifies to 128(n+1)μs.
If the sound register is changed while audio is being output, the change will not become effective until the next negative or positive transition of the audio signal.
|The 2636 datasheet is misleading. It says that the horizontal reset period is normally 63.5μs. That is correct for an NTSC system, but for PAL it is 64μs. Both the horizontal reset period and a number of audio output frequencies have been verified on a Voltmace Database using a Hantek DSO5102P oscilloscope.|
See PVI audio frequency chart for a table of frequencies attainable.
Analogue to digital conversionEdit
Two analogue to digital converters in the PVI are used to determine the position of the analogue joysticks. External circuitry driven from the processor's flag output is used to select input from either the horizontal or the vertical potentiometers.
The conversion process occurs during the active part of the video scan. The resulting digital values must be read from $1FCC and $1FCD during the vertical reset period to get a valid result.