Programmable Logic/VHDL General Syntax

Programmable Logic

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VHDL's syntax is derived from ADA. It is strongly typed and case insensitive.

Identifiers

An identifier in VHDL must begin with a letter and can be any combination of letters, digits, and underscore (_).

Comments

A comment in VHDL is denoted with a "--":

-- Assign the current value to the next state value
sQ_next <= sQ;

Everything after the "--" to the end of the line is considered a comment.

-- This is a valid comment
sQ_next <= sQ; -- This is also a valid comment

Keywords

The following words are VHDL keywords and cannot be used for identifiers (signal names, process names, entity names, etc...)

Top

VHDL 1987

This is an incomplete list...

and, or, nor, xor, not, architecture, entity, is, process, procedure,
function, type, subtype, array, begin, end, if, elsif, end, case, when,
others, configuration, package, constant, signal, variable, component,
label, port, generic, all, nand, nor, abs, generate, in, out, inout,
buffer, linkage, bus, library, null, loop, for, body, to, downto

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VHDL 1993

VHDL 1987 keywords and:

group, impure, inertial, literal, postponed, pure, reject, rol, ror,
shared, sla, sll, sra, srl, unaffected, xnor

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VHDL 2000

VHDL 1993 and 1987 keywords, additionally:

generate map, access, mod, severity, units, after, until, alias, guarded,
use, new, disconnect, next, protected, attribute, record, of, register, on,
block, exit, open, rem, transport, report, file, return

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VHDL 2002

VHDL 1993, 1987 and 2000 keywords, additionally:

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VHDL 2008

VHDL 1993, 1987, 2000 and 2002 keywords, additionally:

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VHDL 2019

VHDL 1993, 1987, 2000, 2002 and 2008 keywords, additionally:

Alphabetical Reference

H

I

if
in
inout
is

J

K

L

label
library
linkage
loop

M

map
mod

N

nand
new
next
nor
not
null

O

of
on
open
or
others
out

P

package
port
procedure
process

Q

R

range
record
register
rem
report
return

S

select
severity
signal
subtype

T

then
to
transport
type

U

units
until
use

V

variable

W

wait
when
while
with

X

xor

Y

Z

links to other references

https://peterfab.com/ref/vhdl/vhdl_renerta/source/vhd00001.htm

abs

Introduction

The abs command in VHDL is a predefined function that returns the absolute value of a numeric argument.

For example, abs(-3) returns 3, and abs(4.5) returns 4.5.

The abs command can be used with any numeric type, such as integer, real, or fixed-point.

Notes

The 1987 version of VHDL saw the introduction of abs.

The abs command is synthesiseable.

synthesizable, Rules, tips, common mistakes, related keywords etc

Syntax

Implementation

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity abs_module is
  port (
    clk : in std_logic;
    reset : in std_logic;
    x : in signed(7 downto 0);
    y : out signed(7 downto 0)
  );
end entity;

architecture rtl of abs_module is
begin
  process (clk, reset)
  begin
    if rising_edge(clk) then -- clock condition
      if reset = '1' then -- synchronous reset condition
        y <= (others => '0'); -- initial value for output signal
      else
        y <= abs(x); -- assign output to absolute value of input
      end if;
    end if;
  end process;
end architecture;

Testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity abs_testbench is
end entity;

architecture sim of abs_testbench is

  -- declare signals for DUT ports
  signal clk : std_logic := '0';
  signal reset : std_logic := '0'; -- added reset signal
  signal x : signed(7 downto 0);
  signal y : signed(7 downto 0);

  -- declare component for DUT
  component abs_module
    port (
      clk : in std_logic;
      reset : in std_logic; -- added reset signal as input port
      x : in signed(7 downto 0);
      y : out signed(7 downto 0)
    );
  end component;

begin

  -- generate clock signal with period of 10 ns
  clk_gen: process
  begin
    clk <= '0';
    wait for 5 ns;
    clk <= '1';
    wait for 5 ns;
  end process;

  -- generate input values for x from -128 to 127
  stim_gen: process
    variable i : integer := -128; -- loop variable
  begin
    wait until rising_edge(clk); -- synchronize with clock
    
    if i = -128 then -- generate a pulse for reset at the beginning of simulation 
      reset <= '1';
      wait for 10 ns;
      reset <= '0';
    end if;

    x <= to_signed(i,8); -- assign input value
    
    i := i + 1; -- increment loop variable
    
    if i = 128 then -- stop when loop variable reaches limit
      wait; -- suspend process
    end if;
    
  end process;

  -- instantiate DUT and connect ports
  dut: abs_module port map (
    clk => clk,
    x => x,
    y => y,
    reset => reset -- added reset signal to port map
  );

  -- observe output values and print messages
  out_obs: process (clk)
    variable exp_y : signed(7 downto 0); -- expected output value
  begin
    if rising_edge(clk) then -- synchronize with clock
      exp_y := abs(x); -- calculate expected output value
      if y = exp_y then -- compare output with expected value
        report "Test passed for x = " & integer'image(to_integer(x)) & ", y = " & integer'image(to_integer(y)); -- print message if match
      else
        report "Test failed for x = " & integer'image(to_integer(x)) & ", y = " & integer'image(to_integer(y)) severity error; -- print message and raise error if mismatch
      end if;
    end if;
  end process;

end architecture;

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access

Introduction

In VHDL, an access type is like a pointer in other programming languages. It allows you to create and manipulate data that is created dynamically during simulation. This means that you can create new data on the fly, and the size of the data doesn’t have to be known in advance.

For example, imagine you want to create a list of numbers, but you don’t know how many numbers there will be. You could use an access type to create a linked list, where each item in the list points to the next item. This way, you can add as many items to the list as you want, without having to know the size of the list beforehand.

Access types are very useful for modeling potentially large structures, like memories or FIFOs, but they are not supported by synthesis tools.

Notes

The 1987 version of VHDL saw the introduction of access.

Not synthesizable

See https://peterfab.com/ref/vhdl/vhdl_renerta/source/vhd00001.htm

Syntax

Usage

-- Incomplete type declaration
type Item;

-- Access type declaration
type Link is access Item;

-- Record type declaration
type Item is record
    Data: string (1 to 6);
    NextItem: Link;
end record;

-- Variable declarations
variable StartOfList, Ptr: Link;
variable Line: LINE;

-- Allocating storage
StartOfList := new Item;
StartOfList.all.Data := "First";
StartOfList.all.NextItem := new Item;
StartOfList.all.NextItem.all.Data := "Second";

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after

Introduction

The VHDL command “after” is used to introduce a delay in the assignment of a signal. It is used to specify the time after which the signal should be assigned a new value. For example, x <= '1' after 10 ns; means that the signal x will be assigned the value '1' after 10 nanoseconds have passed.

Notes

The 1987 version of VHDL saw the introduction of after.

Not Synthesisable.

Delays are not supported in functions.

It is important to note that the “after” command has to do with the delay model. In the default VHDL inertial delay, your second “slower” signal assignment statement cancels the future update of the first. You could schedule multiple updates in one statement to correct this, for example: x <= '1' after 10 ns, '0' after 20 ns;.

see http://gmvhdl.com/delay.htm

Syntax

Usage
x <= '1' after 10 ns;

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alias

Introduction

Aliases, are alternative names for existing objects, such as signals, variables, constants, types, etc. Aliases can be useful for making your code more readable, avoiding name conflicts, or accessing parts of an array or a record.

You can also use a special syntax << ... >> to create external names, which are aliases that can access objects in other design units or hierarchy levels

Notes

The 1987 version of VHDL saw the introduction of alias.

Aliases are local to the declarative region where they are defined, and they cannot be redefined or overridden.

Aliases cannot be used as targets of assignments.

Aliases can be used in any place where the original name can be used, such as expressions, statements, or subprogram calls.

See https://peterfab.com/ref/vhdl/vhdl_renerta/mobile/source/vhd00003.htm

Syntax

Usage

alias alias_name : alias_type is object_name;


alias duv_data_bus is <<signal .tb.duv_rtl.data_bus : std_ulogic_vector (0 to 15)>>; -- create an alias duv_data_bus for the signal data_bus in the component duv_rtl in the entity tb

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all

Introduction

The keyword "all" in a context declaration is a way to specify a set of libraries, packages, and entities that are used in a design unit.

For example, you can write:

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

This means that all the design units that reference this context will have access to the ieee library and the packages std_logic_1164 and numeric_std. The keyword "all" in this case means that all the design units in the current working library can use this context.

Alternative

Since VHDL-2008, the keyword "all" is used to indicate that the sensitivity list of a process should be inferred by the tool, rather than explicitly specified by the designer.

The sensitivity list is a list of signals that trigger the execution of the process when they change their values.

For example, consider the following process that implements a D flip-flop with asynchronous reset:

process (i_clk, i_rst)
begin
 if i_rst = '1' then
  q <= '0';
 elsif rising_edge(i_clk) then
  q <= d;
 end if;
end process;

The sensitivity list of this process is (i_clk, i_rst), which means that the process will run whenever i_clk or i_rst changes. However, we can also use the keyword "all" to let the tool infer the sensitivity list for us:

process (all)
begin
 if i_rst = '1' then
  q <= '0';
 elsif rising_edge(i_clk) then
  q <= d;
 end if;
end process;

This is equivalent to the previous process, as the tool will automatically determine that i_clk and i_rst are the only signals that affect the behavior of the process.

Using the keyword "all" can be convenient and less error-prone, as it avoids the need to manually update the sensitivity list when adding or removing signals from the process.

Some tools may not support this feature, or may generate different results depending on the sensitivity list inference algorithm so check the tool documentation and verify the synthesis and simulation results before using the keyword "all" in a clocked process.

Notes

The 1987 version of VHDL saw the introduction of all.

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and

Introduction

This keyword is used to represent the logical AND operation, which is a basic building block in digital logic circuits.

The `AND` operator performs a bitwise AND operation if the operands are vectors (arrays of bits like std_logic_vector) or performs a logical AND operation if the operands are of type bit or boolean.

If all inputs are ‘1’, the result is ‘1’. Otherwise, the result is ‘0’.

This behavior mimics the functionality of an AND gate in digital electronics.

Notes

The 1987 version of VHDL saw the introduction of and.

see

https://fpgatutorial.com/vhdl-logical-operators-and-signal-assignments-for-combinatorial-logic/

Syntax

Usage
signal A, B, C : std_logic; ... C <= A AND B; In this example, signal `C` will be ‘1’ if both `A` and `B` are ‘1’. Otherwise, `C` will be ‘0’.

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architecture

Introduction

The term "Architecture" assumes a pivotal role. It serves as a formal blueprint associated with an entity declaration, tasked with elucidating the internal organization and operation of a design entity. In essence, an architecture delineates the behavior, data flow, or structural composition of the design entity with precision and rigor. This technical construct finds utility in describing the intricate relationships between input and output ports within a design, encompassing two primary components: declarations and concurrent statements. Declarations encompass various elements, including types, signals, constants, subprograms, components, and groups, while concurrent statements articulate how inputs interact with outputs, with diverse statement types allowing for flexibility in expressing design functionality. Architecture, in the context of VHDL, embodies a systematic and unambiguous approach to defining the fundamental characteristics of digital systems, laying the foundation for their subsequent implementation and analysis.

The architecture is used to detail the behavior, data flow, or structure of a design entity.

An architecture linked to an entity primarily delineates the inner relationships between the input and output ports of the entity. It consists of two primary components: declarations and concurrent statements.

The declarative part of an architecture encompasses various types of declarations, such as types, signals, constants, subprograms (functions and procedures), components, and groups. Detailed information on each of these can be found in their respective topics.

Concurrent statements, on the other hand, describe how inputs relate to outputs within the architecture. These relationships can be expressed through diverse types of statements, including concurrent signal assignments, process statements, component instantiations, concurrent procedure calls, generate statements, concurrent assertion statements, and block statements. These statements can be written in various styles, such as structural, dataflow, behavioral (functional), or mixed, depending on the intended design.

Structural descriptions rely on component instantiation and generate statements, enabling the creation of hierarchical projects that range from simple gates to intricate components, encompassing entire subsystems. These components connect through ports, as illustrated in Example 1 for a BCD decoder.

Dataflow descriptions employ concurrent signal assignment statements. Each statement can activate when any of its input signals change, describing the circuit's behavior and structure, as showcased in Example 2.

In contrast, a behavioral description, as demonstrated in Example 3, includes only one or more processes, each containing sequential statements. This approach focuses solely on the expected functionality of the circuit, without specifying hardware implementation details.

A mixed architecture description, as seen in Example 4, combines both behavioral and structural elements within the same architecture body.

Notes

The 1987 version of VHDL saw the introduction of architecture.

An entity can have multiple architectures, but an architecture cannot be assigned to different entities.

An architecture must be associated with an entity.

All declarations within an entity are entirely visible and accessible within any architecture assigned to that entity.

Different types of statements, such as processes, blocks, concurrent signal assignments, component instantiations, etc., can coexist within the same architecture.

Syntax

Usage

Example 1:

architecture Structure of Decoder_bcd is
  signal S: Bit_Vector(0 to 1);
  component AND_Gate
    port(A,B:in Bit; D:out Bit);
  end component;
  component Inverter
    port(A:in Bit; B:out Bit);
  end component;
begin
   Inv1:Inverter port map(A=>bcd(0), B=>S(0));
   Inv2:Inverter port map(A=>bcd(1), B=>S(1));
   A1:AND_Gate port map(A=>bcd(0), B=>bcd(1), D=>led(3));
   A2:AND_Gate port map(A=>bcd(0), B=>S(1), D=>led(2));
   A3:AND_Gate port map(A=>S(0), B=>bcd(1), D=>led(1));
   A4:AND_Gate port map(A=>S(0), B=>S(1), D=>led(0));
end Structure;

Example 2:

architecture Dataflow of Decoder_bcd is
begin
   led(3) <= bcd(0) and bcd(1);
   led(2) <= bcd(0) and (not bcd(1));
   led(1) <= (not bcd(0)) and bcd(1);
   led(0) <= (not bcd(0)) and (not bcd(1));
end Dataflow;

Example 3:

architecture procedural of Decoder_bcd is
  signal S: bit_vector (3 downto 0);
begin
   P1: process (bcd, S)
   begin
     case bcd is
         when "00" => S <= "0001" after 5 ns;
         when "01" => S <= "0010" after 5 ns;
         when "10" => S <= "0100" after 5 ns;
         when "11" => S <= "1000" after 5 ns;
     end case;
     led <= S;
   end process;
end procedural;

Example 4:

architecture Mixed of Decoder_bcd is
  signal S: Bit_Vector(0 to 2);
  component Inverter
    port(A: in Bit; B: out Bit);
  end component;
begin
  Inv1: Inverter port map (A=>bcd(0), B=>S(0));
  Inv2: Inverter port map (A=>bcd(1), B=>S(1));
  P: process (S, bcd)
  begin
    led(0) <= S(0) and S(1) after 5 ns;
    led(1) <= S(0) and bcd(1) after 5 ns;
    led(2) <= bcd(0) and S(1) after 5 ns;
    led(3) <= bcd(0) and bcd(1) after 5 ns;
  end process;
end Mixed;

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array

Introduction

Introduction to the Keyword "Array" in VHDL:

In VHDL, the keyword "Array" is a versatile data type to structure and organise data. In VHDL, an array is formally defined as a type whose value consists of elements of the same subtype, making it ideal for managing homogeneous data sets. What distinguishes each element within an array is an index (or indices, for multidimensional arrays) associated with it. These indices are required to be values of a discrete type and must fall within the specified index range.

In simpler terms, an array is like a container that holds elements of a consistent type, and each element is uniquely identified by its index. The number of indices directly corresponds to the number of dimensions; for example, a one-dimensional array has one index, while a two-dimensional array has two.

Arrays in VHDL come in two flavors: constrained and unconstrained. A constrained array has a fixed size, determined either by a discrete type mark or a specified range. In contrast, an unconstrained array does not have a predefined size; its size is only determined when you declare an object of that type.

For instance, VHDL's Package STANDARD includes predefined unconstrained array types like STRING and BIT_VECTOR. These arrays are widely used, with STRING elements indexed by positive values and BIT_VECTOR elements indexed by natural values.

Arrays in VHDL can be manipulated using various techniques such as indexing, concatenation, aggregates, and slices. These methods provide flexibility in accessing and assigning values to array elements, making them a crucial component of VHDL programming.

It's worth noting that while arrays are a powerful tool in VHDL, not all synthesis tools support multidimensional arrays. There are exceptions, such as two-dimensional "vectors of vectors," and some synthesis tools allow limited support for two-dimensional arrays.

In summary, arrays in VHDL are fundamental data structures that allow you to efficiently manage and manipulate collections of data, making them a key element in VHDL programming.

Notes

The 1987 version of VHDL saw the introduction of array.

Syntax

Usage

type type_name is array (range) of element_type

type type_name is array (type range <>) of element_type

type Real_Matrix is array (1 to 10) of REAL;
type BYTE is array (0 to 7) of BIT;
type Log_4_Vector is array (POSITIVE range 1 to 8, POSITIVE range 1 to 2) of Log_4;
type X is (LOW, HIGH);
type DATA_BUS is array (0 to 7, X) of BIT;

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assert

Introduction

In VHDL, the assert command is used to validate assumptions or conditions within your code. When the condition specified in the assert statement is false, an error message is generated, and the simulation can be halted, paused, or continue based on the severity level specified.

This feature is useful in VHDL for debugging, as it helps identify errors in the simulation phase, reducing the risk of issues in actual hardware.

Notes

The 1987 version of VHDL saw the introduction of assert.

Not Synthesisable.

Syntax The general syntax for the assert command is

assert <condition>
report "<message>"
severity <level>;

e.g.

process
begin
    assert (clk /= '0')
    report "Clock signal should not be zero"
    severity error;
end process;

Each component of this syntax serves a specific purpose:

<condition>: A boolean expression that the designer expects to be true. If false, the assert command will activate.
<message>: (Optional) A string that provides additional information about the condition, helping to identify the reason for failure.
<level>: (Optional) Specifies the severity level of the assertion failure, which controls how the simulation responds. Severity levels include:
- note: Minor information; simulation continues.
- warning: Indicates potential issues; simulation continues.
- error: A critical problem; simulation continues but indicates a serious issue.
- failure: Terminates the simulation, representing a fatal error.

Why Use the Assert Command?

Using assert commands enhances the reliability and maintainability of VHDL code. With assertions, designers can ensure that:

Key assumptions hold true throughout the design.
Corner cases are effectively handled.
Critical sections of the design meet expected criteria during simulations.

Assertions are particularly useful in:

Testbenches, to check expected values.
Design specifications, to enforce conditions on inputs and outputs.
Safety-critical applications, to prevent unexpected behaviors.

Implementation
assert not (S= '1' and R= '1') report "Both values of signals S and R are equal to '1'" severity ERROR;

Testbench

 signal test_input : std_logic := '1';
 signal test_output : std_logic;

 test_process : process
 begin
    -- Some logic to simulate a condition
    test_output <= not test_input;
    wait for 10 ns;
    
    -- Assert that the output is as expected
    assert (test_output = '0')
    report "Test failed: test_output was not '0'"
    severity failure;
end process test_process;

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attribute

Introduction

Notes

The 1987 version of VHDL saw the introduction of attribute.

Syntax

Usage
-- Code

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begin

Introduction

Notes

The 1987 version of VHDL saw the introduction of begin.

Syntax

Usage
-- Code

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block

Introduction

Notes

The 1987 version of VHDL saw the introduction of block.

Syntax

Usage
-- Code

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body

Introduction

Notes

The 1987 version of VHDL saw the introduction of body.

Syntax

Usage
-- Code

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buffer

Introduction

Notes

The 1987 version of VHDL saw the introduction of buffer.

Syntax

Usage
-- Code

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bus

Introduction

Notes

The 1987 version of VHDL saw the introduction of bus.

Syntax

Usage
-- Code

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case

Introduction

Notes

The 1987 version of VHDL saw the introduction of case.

Syntax

Usage
-- Code

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component

Introduction

Notes

The 1987 version of VHDL saw the introduction of component.

Syntax

Usage
-- Code

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configuration

Introduction

Notes

The 1987 version of VHDL saw the introduction of configuration.

Syntax

Usage
-- Code

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constant

Introduction

Notes

The 1987 version of VHDL saw the introduction of constant.

Syntax

Usage
-- Code

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disconnect

Introduction

Notes

The 1987 version of VHDL saw the introduction of disconnect.

Syntax

Usage
-- Code

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downto

Introduction

Notes

The 1987 version of VHDL saw the introduction of downto.

Syntax

Usage
-- Code

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else

Introduction

Notes

The 1987 version of VHDL saw the introduction of else.

Syntax

Usage
-- Code

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elsif

Introduction

Notes

The 1987 version of VHDL saw the introduction of elsif.

Syntax

Usage
-- Code

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end

Introduction

Notes

The 1987 version of VHDL saw the introduction of end.

Syntax

Usage
-- Code

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entity

Introduction

Notes

The 1987 version of VHDL saw the introduction of entity.

Syntax

Usage
-- Code

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exit

Introduction

Notes

The 1987 version of VHDL saw the introduction of exit.

Syntax

Usage
-- Code

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file

Introduction

Notes

The 1987 version of VHDL saw the introduction of file.

Syntax

Usage
-- Code

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for

Introduction

Notes

The 1987 version of VHDL saw the introduction of for.

Syntax

Usage
-- Code

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function

Introduction

Notes

The 1987 version of VHDL saw the introduction of function.

Syntax

Usage
-- Code

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generate

Introduction

Notes

The 1987 version of VHDL saw the introduction of generate.

Syntax

Usage
-- Code

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generic

Introduction

Notes

The 1987 version of VHDL saw the introduction of generic.

Syntax

Usage
-- Code

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guarded

Introduction

Notes

The 1987 version of VHDL saw the introduction of guarded.

Syntax

Usage
-- Code

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if

Introduction

Notes

The 1987 version of VHDL saw the introduction of if.

Syntax

Usage
-- Code

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in

Introduction

Notes

The 1987 version of VHDL saw the introduction of in.

Syntax

Usage
-- Code

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inout

Introduction

Notes

The 1987 version of VHDL saw the introduction of inout.

Syntax

Usage
-- Code

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is

Introduction

Notes

The 1987 version of VHDL saw the introduction of is.

Syntax

Usage
-- Code

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label

Introduction

Notes

The 1987 version of VHDL saw the introduction of label.

Syntax

Usage
-- Code

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library

Introduction

Notes

The 1987 version of VHDL saw the introduction of library.

Syntax

Usage
-- Code

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linkage

Introduction

Notes

The 1987 version of VHDL saw the introduction of linkage.

Syntax

Usage
-- Code

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loop

Introduction

Notes

The 1987 version of VHDL saw the introduction of loop.

Syntax

Usage
-- Code

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map

Introduction

Notes

The 1987 version of VHDL saw the introduction of map.

Syntax

Usage
-- Code

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mod

Introduction

Notes

The 1987 version of VHDL saw the introduction of mod.

Syntax

Usage
-- Code

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nand

Introduction

Notes

The 1987 version of VHDL saw the introduction of nand.

Syntax

Usage
-- Code

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new

Introduction

Notes

The 1987 version of VHDL saw the introduction of new.

Syntax

Usage
-- Code

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nor

Introduction

Notes

The 1987 version of VHDL saw the introduction of nor.

Syntax

Usage
-- Code

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not

Introduction

Notes

The 1987 version of VHDL saw the introduction of not.

Syntax

Usage
-- Code

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null

Introduction

Notes

The 1987 version of VHDL saw the introduction of null.

Syntax

Usage
-- Code

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of

Introduction

Notes

The 1987 version of VHDL saw the introduction of of.

Syntax

Usage
-- Code

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on

Introduction

Notes

The 1987 version of VHDL saw the introduction of on.

Syntax

Usage
-- Code

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open

Introduction

Notes

The 1987 version of VHDL saw the introduction of open.

Syntax

Usage
-- Code

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or

Introduction

Notes

The 1987 version of VHDL saw the introduction of or.

Syntax

Usage
-- Code

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others

Introduction

Notes

The 1987 version of VHDL saw the introduction of others.

Syntax

Usage
-- Code

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out

Introduction

Notes

The 1987 version of VHDL saw the introduction of out.

Syntax

Usage
-- Code

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package

Introduction

Notes

The 1987 version of VHDL saw the introduction of package.

Syntax

Usage
-- Code

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port

Introduction

Notes

The 1987 version of VHDL saw the introduction of port.

Syntax

Usage
-- Code

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procedure

Introduction

Notes

The 1987 version of VHDL saw the introduction of procedure.

Syntax

Usage
-- Code

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process

Introduction

Notes

The 1987 version of VHDL saw the introduction of process.

Syntax

Usage
-- Code

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range

Introduction

Notes

The 1987 version of VHDL saw the introduction of range.

Syntax

Usage
-- Code

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record

Introduction

Notes

The 1987 version of VHDL saw the introduction of record.

Syntax

Usage
-- Code

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register

Introduction

Notes

The 1987 version of VHDL saw the introduction of register.

Syntax

Usage
-- Code

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rem

Introduction

Notes

The 1987 version of VHDL saw the introduction of rem.

Syntax

Usage
-- Code

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report

Introduction

Notes

The 1987 version of VHDL saw the introduction of report.

Syntax

Usage
-- Code

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return

Introduction

Notes

The 1987 version of VHDL saw the introduction of return.

Syntax

Usage
-- Code

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select

Introduction

Notes

The 1987 version of VHDL saw the introduction of select.

Syntax

Usage
-- Code

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severity

Introduction

Notes

The 1987 version of VHDL saw the introduction of severity.

Syntax

Usage
-- Code

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signal

Introduction

Notes

The 1987 version of VHDL saw the introduction of signal.

Syntax

Usage
-- Code

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subtype

Introduction

Notes

The 1987 version of VHDL saw the introduction of subtype.

Syntax

Usage
-- Code

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then

Introduction

Notes

The 1987 version of VHDL saw the introduction of then.

Syntax

Usage
-- Code

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to

Introduction

Notes

The 1987 version of VHDL saw the introduction of to.

Syntax

Usage
-- Code

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transport

Introduction

Notes

The 1987 version of VHDL saw the introduction of transport.

Syntax

Usage
-- Code

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type

Introduction

Notes

The 1987 version of VHDL saw the introduction of type.

Syntax

Usage
-- Code

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units

Introduction

Notes

The 1987 version of VHDL saw the introduction of units.

Syntax

Usage
-- Code

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until

Introduction

Notes

The 1987 version of VHDL saw the introduction of until.

Syntax

Usage
-- Code

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use

Introduction

Notes

The 1987 version of VHDL saw the introduction of use.

Syntax

Usage
-- Code

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variable

Introduction

Notes

The 1987 version of VHDL saw the introduction of variable.

Syntax

Usage
-- Code

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wait

Introduction

Notes

The 1987 version of VHDL saw the introduction of wait.

Syntax

Usage
-- Code

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when

Introduction

Notes

The 1987 version of VHDL saw the introduction of when.

Syntax

Usage
-- Code

Top

while

Introduction

Notes

The 1987 version of VHDL saw the introduction of while.

Syntax

Usage
-- Code

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with

Introduction

Notes

The 1987 version of VHDL saw the introduction of with.

Syntax

Usage
-- Code

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xor

Introduction

Notes

The 1987 version of VHDL saw the introduction of xor.