Digital Circuits/I-O Interfacing

Unused InputsEdit

Digital devices can only deal with signals within well defined logic levels. Signals in between these levels are said to be "floating" and can cause spurious and unpredicatable behaviour. It is important to connect all inputs of a logic device to "high" or "low" if they are not being used as an input, to prevent the floating input affecting the rest of circuit, or causing unnecessary power drains.

The logic level that should be applied to the input depends on the device, and what the designer wishes an unused input to signify. For example, an OR gate would have any unused inputs tied low, as this prevents that input from affecting the output.

A simple solution is to connect the inputs of a gate together. However, this increases the capacitative load of the circuit driving the inputs and if the device contains bipolar elements, increases the DC current drain.

A better solution is to connect the unused inputs to the relevant power rails. If a logical low is needed, connect the input directly to ground, if a high is required, connect it to the positive rail either directly or through a series resistor.

A very similar layout can also be used to create transmission gates.

Slow Input Edge TransitionsEdit

Ground BounceEdit

Ground bounce is a transient voltage difference between the ground reference potential on the device die and the external ground level at the device's ground pin. This oscillation is caused by the inductance of the thin wires (bond wires) connecting the die to the leadframe of the device causing a current surge upon sudden voltage changes, such as caused by a logic transition.

Ground bounce is one of the primary causes of glitches and spurious transitions in high-speed logic and can cause significant signal degradation between logic devices. This effect is most pronounced at multiple simultaneous transitions, where the joint voltage changes cause a larger current to be induced. This has lead to ground bounce also being called Simultaneous Switching Noise.

Below is a graph showing a typical (although simplified) ground bounce in a high-speed CMOS logic device. Different logic classes and manufacturing techniques have different ground bounce characteristics. The device-external properties such as circuit board geometry also have an effect. You should always check the relevant datasheet if ground bounce is expected to be a problem.

Capacative Output LoadingEdit

Bus ContentionEdit

Bus-hold CircuitsEdit