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In this book Chip Design we tell how to build an integrated circuit ("chip") by integrating billions of transistors to achieve an application. An application could be suiting a particular requirement like microprocessor, router, cell phone,etc. An integrated circuit designed for a specific application is called as ASIC (Application Specific Integrated Circuits).

Today's ASIC Chips are pretty complex, packed with larger chunk of transistors targeted to a specific manufacturing process for fabricating the integrated circuits, in a sub nanometer regime, involving many challenges like knowledge of various protocols, architectures, models, formats, standards, knowledge about CMOS logic, Digital Design concepts, taming the EDA tool for the various design requirements like area, timing, power, thermal, noise, routability, lithography aware, knowledge about various variabilities like channel length, Vt, line width variations, lens aberrations, IR drop effects, inter-die and intra die-variations, effects, and various noise-effects like package noise, EMI noise, power grid noise, cross-talk noise, and ability to test and validate and know to model and characterize all these effects upfront in the design-phase, steps to increase profitability curve, with short span of time-to market to minimize the risk and maximize the predictability and an modular approach to success. Now let's delve in to the "Art of Chip Designing".

That is a lot of technical jargon, but there is nothing to worry about. You will soon learn what that means, and understand the concepts behind chip designing.


Before Designing a Chip? Need to Brain StormEdit

  • What market is the Chip targeted for?
  • What are the Protocols involved in the Chip?
  • What is going to be our Processor/Bus Architectures?
  • What is the power/IR-drop/timing/area/yield targets and how to budget it in the Chip?
  • What is the process in which the Chip is going to be manufactured?
  • What are the various third party IP's/Memory requirements?
  • What is our design flow, EDA tools and methodology involved?
  • What is the estimated Chip cost?
  • Above all, the bottom line of any business model is money. What is our Profit model? What is our estimated ROI (Return of investment)?

Analogy of Chip Design Architecture Vs Building Architecture.Edit

Why an Analogy with Building Architecture? To understand the concepts of Chip designing in a better way, as we are very familiar with Building Architecture, then it will be easy for us to map Chip Design architecture.

VLSI (Very large scale Integration) flow was evolved similar to the flow involved in Building Construction. Now let us delve in to the construction flow to better understand the VLSI Chip design flow development.

Whenever we start to construct a building, we will have an architecture, how the building should look like, the exterior looks, etc. Similar to that we will be designing an architecture in the chip-design, based on the requirement of the product, what the product is addressed for and whom to serve what needs -the so called specification- of the different modules.

Now lets go in to the implementation part of both the Building & Chip.

We at first come with the floorplan of the building, similarly we come with the floorplan of the Chip. Based on the connectivity/accessibility/vaasthu we place our rooms, similarly we have the constraints to place the blocks. Like we build the building with bricks, windows and other modules, for Chip Design we have component libraries, which are like pre-designed bricks, for a specific functionality.

Now let us try to understand the power-structure or electrical connectivity in our building. Initially we have an electrical plan for our building, where we have a requirement that all our electrical gadgets needs to get power. Similar to that we have a Chip power requirement. The required power is supplied through the power-pads, over a ring-like topology to have a uniform distribution across all corners of the chip, and the supply has to reach all the standard-cells (bricks for Chip-Designing), this is called as power-grid topology in the Chip-Design. Now the requirement is how well we design our Power-grid to reduce the IR-drop, so that our standard-cells get proper power requirement.

I would not make justice if I don't discuss about clock and clock-tree in the Chip-Design flow. We have synchronous and asynchronous (more difficult to test and verify) ways of designing. The majority of chips follow a synchronous design, for which Static Timing Analysis is possible. For the relevancy of the flops, the clock signal from the crystal should reach at the same time -or within some skew targets- to different components within the chip. In order to make this happen, a step called clock-tree is performed after power-grid is created.

Let us try now to visualize the concept behind Place & Route in Chip Design, where the different components of the chip are physivally placed and their pins properly inter-connected. To have a better understanding of this concept, let us assume a society where people speaking different languages are living together, and let us visualize how people talking the same language will tend to end up living in the same neighborhood, forming separated communities and making the communication between people much easier. In a similar way, in chip-designing, standard-cells having strong relationships are placed closer in the placement flow, forming separated areas. This process is called as regioning. Now, within the regions, the standard-cells which are really sharing data have to be placed close-by so that their timings match and are optimized. This step is called placement, while defining the connectivity across the standard-cells is called as routing, and the challenge is having optimized or reduced wire-lengths.

Now let us try to understand the concept behind Signal Integrity (SI) in the Chip-Design, often called as SI Effect. As our processes are shrinking day by day, and our silicon-realestate is costly, we try to accommodate more and more standard-cells in a limited area, so the cells are placed in very close proximity, and the switching of one cell can have an impact over the others' behaviour, which can make the path to be faster or slower. This issue is called as signal-integrity. So similar way in our construction in order to maintain the integrity with in the house (neighbour free-zone), within the limited zone of modurality, we try to create fences across buildings, similarly we can think of a concept called as Shielding, the high frequency signal net with the power-nets running across. We perform spacing across the buildings, similar way we can perform spacing across the nets, which are in close proximities.

In order to validate the silicon from the manufacturability issues, the concept in the Chip Designing is Design for Test(DFT). One of the DFT techniques is scan-chain. To understand the concept of the scan-chain, we can visualize that we have a front-door entry and a back-door exit, and a person passes from the front-door and exits from the back-door exit of the building, that we are sure that there is no blocking within the rooms in the building, to make that person stuck , similar to this analogy the flip-flops are connected together creating a scan-chain and test-input values are passed from the scan-chain input of the chip and expected data is visualized in the scan-chain output of the chip, then the assumption is the chip is free from manufacturability issues like stuck-at faults(stuck-at one or stuck at zeros).

VLSI Design FlowEdit

Step 1: Prepare a Requirement Specification

Step 2: Create a Micro-Architecture Document.

Step 3: RTL(Register Transfer Level) Design & Development of IP's(Intellectual Property)

Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.

Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL

Step 4b: Perform Property Checking , to verify the RTL implementation and the specification understanding is matching.

Step 4c: Perform Clock Domain Crossing check, to verify that proper synchronization of control/data is there to ensure reliable cross domain data transfers.

Some people use "logical effort" to estimating the latency in the critical path of a CMOS circuit, and hence the maximum possible speed of the circuit.[1]

Step 5: Prepare the Design Constraints file (clock definitions(frequency/uncertainty/jitter),I/O delay definitions, Output pad load definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an SDC file(Synopsys constraint file, specific to Synopsys synthesis Tool (Design Compiler))

Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which synthesis needs to be targeted for, which has the functional/timing information available for the standard-cell library and the wire-load models for the wires based on the fanout length of the connectivity), RTL files and the Design Constraint files, So that the Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet the design-constraints requirements. After performing synthesis, as a part of the synthesis flow, need to build scan-chain connectivity based on the DFT(Design for Test) requirement, the synthesis tool (Test-compiler), builds the scan-chain.

Step 7: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT) after synthesis.

Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting the power targets.

Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the design is meeting the functional requirements.

Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that the synthesis Tool has not altered the functionality.

Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format) file and synthesized netlist file, to check whether the Design is meeting the timing-requirements.

Step 7e: Perform Scan-Tracing , in the DFT(Design for Test) tool, to check whether the scan-chain is built based on the DFT requirement.

Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog format) and the SDC (constraints file) is passed as input files to the Placement and Routing Tool to perform the back-end Activities.

Step 9: The next step is floor-planning. Floor-planning means placing the IP's based on the connectivity,placing the memories, Create the pad ring (also called the pad frame),[2][3][4][5] placing the Pads (Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper accessibility for Package routing), meeting the SSN requirements (Simultaneous Switching Noise) that when the high-speed bus is switching that it doesn't create any noise related activities, creating an optimised floorplan, where the design meets the utilization targets of the chip.

Step 9a : Release the floor-planned information to the package team, to perform the package feasibility analysis for the pad-ring .

Step 9b: To the placement tool, rows are cut, blockages are created where the tool is prevented from placing the cells, then the physical placement of the cells is performed based on the timing/area requirements.The power-grid is built to meet the power-target's of the Chip .

Step 10: The next step is to perform the Routing., at first the Global routing and Detailed routing, meeting the DRC(Design Rule Check) requirement as per the fabrication requirement.

Step 11: After performing Routing then the routed Verilog netlist, standard-cells LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is generated.

Step 12: Check whether the Design is meeting the requirements (Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement and Routing step.

Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design has met the power targets.

Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the design is meeting the functional requirement .

Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the place & route Tool has not altered the functionality.

Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file, to check whether the Design is meeting the timing-requirements.

Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built based on the DFT requirement, Perform the Fault-coverage with the DFT tool and Generate the ATPG test-vectors.

Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)

Step 12g: Perform DRC(Design Rule Check) verification called as Physical-verification, to confirm that the design is meeting the Fabrication requirements.

Step 12h: Perform LVS(Layout vs Schematic) check, a part of the verification which takes a routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call it SPICE-S) and compare that the two are matching.

Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is meeting the ERC requirement.

Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and proper guarding is there in case if we have both analog and digital portions in our Chip. We have separate Power and Grounds for both Digital and Analog Portions, to reduce the Substrate-noise.

Step 12k: Perform separate STA(Static Timing Analysis) , to verify that the Signal-integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF file(parasitics including coupling capacitances values), are fed to the tool. This check is important as the signal-integrity effect can cause cross-talk delay and cross-talk noise effects, and hinder in the functionality/timing aspects of the design.

Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand the static and dynamic power-drops with in the design and the IR-drop is with-in the target limits.

Step 13: Once the routed design is verified for the design constraints, then now the next step is chip-finishing activities (like metal-slotting, placing de-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which the fab can understand, GDS file.

Step 15: After the GDS file is released , perform the LAPO check so that the database released to the fab is correct.

Step 16: Perform the Package wire-bonding, which connects the chip to the Package.

Deeper to Chip ArchitectureEdit

This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.

  • What is the targeted market for this Chip.
  • What are the competitor's to this Chip and Market Requirement and ROI
  • What is the Fabrication Unit the Chip is targeted for?
  • What is the Success rate and Yield numbers achieved in the Fabrication Unit
  • What is the technology Process targeted for
  • What is the correlation of the library models w.r.t. Silicon
  • What are the various Protocols the Chip is going to address
  • Hardware & Software Parti-tioning.
  • What is the processor/micro-controller suitable for this application.
  • What is the bus-architecture targeted
  • What are the performance targets for this bus architecture
  • What are the various Interfaces the Chip is having
  • Is the design going to be in single Vt or with Multi-Vt design
  • Is using Embedded macro's right choice or Memory Macros
  • What are the IP's are going to be Re-used
  • What are the IP's going to Hard-macro's
  • What is the Verification Status and corner-case coverage of the I.P's
  • What is the Die-size targeted/Estimated for the Chip
  • What are the Power targets
  • Is Power Management Unit a requirement in the chip to reduce Dynamic power
  • What are the mechanisms followed to reduce the leakage power
  • Is Module enables/clock-gating a part of the Methodology
  • Are resets going to synchronous or asynchronous
  • What are the various Synchronous Mechanisms for data-transfer's
  • How many clock-domains required for the Chip
  • How many PLL's are required or single PLL sufficient for all the clocks required
  • What is the thought process behind PAD's Is LVTTL/SSTL pads
  • Is the package going to wire-bond or Flip-chip
  • Methodology for Optimal Power-grid design
  • What are the noise reducing Mechanisms in case of analog integration
  • Is there any requirement of speed monitor's or process checking blocks
  • What is the type of fuses used laser fuse or effuses
  • Is there any requirement of Fib Cells in the Design
  • What are the mechanisms used to handle ESD
  • what is the reliability target of the Chip and how it is addressed
  • What are the Mechanisms used for Yield improvement
  • Is the chip tested at at-speed test
  • How much Memory-map is allocated for the IP's
  • What is the metric for spare-gates in the Chip for ECO's
  • Are repairable memories required
  • What is the tester targeted and the requirement to the Chip in terms of Scan-chain
  • Is test-vector compression mechanism's a requirement
  • What is the PLL(Phase Locked Loop) performance in terms of Jitter
  • What is the Interrupt handling mechanism within the Chip.
  • What is the ROM-Code for the Chip.
  • What are the Chip utilization targets
  • Will the chip be routable or any requirement for special libraries with different routing tracks.
  • What is the Methodology for tools and versions
  • What is the Version control mechanism planned for data handling across multi Geographical Environments.
  • What are the sign-off criteria for the Chip
  • What are the frequency targets for the Chip.
  • Is there room for further revisions of the Chip.
  • If the Chip has DDR/SDR interface is there any requirement for DLL.
  • What are the limitations of the Tools in terms of Complexity/run-times/turn-around times/Computation Power requirements.
  • What is the Mechanisms/Steps taken for the various Variability in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.

Thought Process Involved in Bus-ArchitecturesEdit

what are various parameters to be looked in to for an optimal System bus architecture in an SoC, in order to have maximum performance possible.

  • System speed is not only dependent on the Processor/Micro-controller but also on the Bus speed the system operates.
  • Contention Prevention mechanism's across multiple drivers.
  • Bus Splitters: Hierarchical Bus structures, based on the speed targets {for example the AMBA bus from ARM, has two bus hierarchy levels : Advanced High Performance Bus[AHB] & Advanced Peripheral Bus[APB]. Split bus architectures has energy efficient transactions and concurrent data transactions over the conventional buses.
  • Reducing latency and crossbar utilization mechanisms.
  • Optimum Bridging Mechanisms for cross data Transfer's among the Buses.
  • Performance Enhancers by having Pipeline mechanism's and steps to prevent Stalling.
  • Arbitration Protocol schemes for shared buses {Fixed Priority Schemes, Round Robin Scheme, * Time Division Multiplexing Schemes}.
  • Mechanisms to reduce bus waiting time.
  • Synchronization mechanism's across the bus
  • Scheduling based on power-profiling.
  • Traffic based Dynamic Voltage and frequency scaling techniques for meeting power-targets.

Implementation Challenges and SolutionsEdit

The metric for today's ASIC Design is on one side of the coin is the maximum number of devices integrated, reduced die-size,optimal power,speed,thermal performance, addressing signal integrity, addressing reliability, enhanced yield techniques, reducing PLL jitters for reliable functionality, testability,integration of analog and digital in single SoC, Lithography friendly DRC, Functionality met, high speed interfaces to memories, the IO fabric, IO buffer analysis and selection, implementation to validate the silicon, ability to in-corporate last minute spec changes/functional & timing bugs Engineering Change Orders, Optimized package feasible, development phases involving multi-geographical multi-site, complex database handling, various models/abstractions/standards/formats/Protocols, advanced process, library characterization modelling silicon, higher degree of EDA tools, design re-use standards, building designs robust enough to deal with EMI noise/package noise/power-ground noise/cross-talk noise/substrate-noise/clock-jitter/process uncertainties/IR-drop/On-chip variation and on other side of the coin, how to address all these issues right from the design stage is the challenge of today's Chip Design Industry.

This tight bonding of integration across the domains/abstractions/tools/designers/process/protocols/standards/design re-use/decision in optimal trade-offs/design know-how's/cross-culture design community needs a modular uniform approach , to bring first pass silicon success. Now let's deal with the Implementation challenges and steps to achieve it in the design-phase.

Complex Database Handling/Multi-site Design & Development As now the designs are development in multi-site environment, as each site has some domain expertise and to use to the fullest it needs multi-site design and development stages, in order to maintain the database handling a proper version control management System (e.g., clearcase) is required to proper align the database , tag it with labels to know the database and finally after designing go through with proper reviews and checklist process to assure the quality of the delivery.

Designing an Optimal Padring Steps involved in designing an optimal padring

Make sure you have corner-pads, across all the corners of the padring This is mainly to have the power-continuity as well as the resistance is less Ensure that the Padring fulfills the ESD requirement, Identify the power-domains,split the domains, Ensure common ground across all the domains. Ensure that the design has sufficient core power-pads. Choose the Drive-strength of the pads based on the current requirements, timing. Ensure that there is separate analog ground and power pads. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O's.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with unconnected inputs, they consume power if the inputs float. Ensure that oscillator-pads are used for clock inputs. In-case if the design requirement for source synchronous circuits make sure that the clock and data pads are of same drive-strength. Breaker-pads are used to break the power-ring, and to isolate the power-structure Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin. Ensure that few pad-filler cells are placed near the corner pads to ease the substrate routing requirements. In case of source synchronous pads, like clock and data going out, Ensure that these pads are on the centre, as the leads at the center of the package is short compared to the leads on the corners of the package, which can reduce the impact of EMI.

Designing for Optimized Area As silicon real-estate is very costly and saving is directly proportional to the company's revenue generation lot of emphasize is to design which has optimal utilization in the area-front. The steps to reduce area are

If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets.

Designing an Optimized floorplan Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently, then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed, estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise.

Designing for Achieving Power-targets As Today's IC design power plays a major-role in the design win, achieving power-targets are the major concern. Some of the design best-practices are Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design, clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enables gives a lot of power-savings. As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage & Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced.

Designing for Achieving Frequency targets. As ASIC designs are today rated by the clock frequency the design can achieve, brings with lot of performance within. The few design strategies to achieve the frequency targets.

Using logic restructuring for the areas to be timing met, Use the useful skew , if permissible by meeting the hold-time requirements. Use register retiming/time-borrowing concepts to meet the design timing requirements Use faster flip-flops for the timing-paths which are timing hungry. Use Low-Vt cells for the paths to meet the timing. Ensuring the design meets the frequency targets by performing STA, across all the functional and test modes , across all the corners, including the derating factors. Make sure that there exists common clock-tree paths and bifurcation happens only at the last-stage, so that the common clock-path can be removed in the delay calculation as over-head in the pessimism removal during de-rating. Incorporate programmable DLL(Delay locked loop) based design, for memory-controller designs, which involves round-trip delays.

Designing for Meeting Signal-integrity targets As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let's see now by what are all the measures we can reduce/solve it.

As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI. Enable SI aware routing , so that the tool takes care for SI Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other Minimize the parallel run-length wires, by inserting buffers.

Designing for Better Yield(DFY/DFM) Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranteeing the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge.

Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it. For via-reliability issues, use redundant vias, to reduce the chances for via-breakage. In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories. Optimal placing of decoupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained.

Designing for Optimal integration of Analog and Digital As today's IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists separate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro's. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion.

Designing for Engineering Change Order As more and more complex the IC design is , and with lot of first time application , is more prone to last minute changes, there should be provision in the design-flow to accommodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO).

Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved.

Designing an Lithography friendly Design Designing for Manufacturability requires validating the design full-filling lithography rules

Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets.

Chip Verification methodologiesEdit

-"Anything that can go wrong - Will"-Murphy

What is my next step to be performed?

Now Lets start with an assumption that anything may go wrong

What are the various areas can things go wrong?

List down the areas in the flow that things can go wrong and derive a methodology to verify at each and every stage. List down all your uncertainties that could potentially happen and how to model it and how to constrain and verify up-front. Explore and re-visit each and every area in the Design flow to cover potential risk

Functional Verification (RT L level , Gate level) Formal Verification Static Timing Analysis Physical Verification Power Simulation Thermal Simulation Noise Simulation Test Simulation Emulation Hardware prototype Hardware Software co-simulation Transistor level Simulation Now lets Venture in to each area and insure it

Functional Verification:

TLM(Transaction Level Modeling) Linting RTL Simulation (Environment involving : stimulus generators, monitors, response checkers, transactors) Gate level Simulation Mixed-signal simulations Regression How Much Did I cover in the functional part - What is my Coverage Metric? and what are the methodologies used?

Is the verification tests covered pin-pointed tests or tests with random seeds to cover all the corner-cases. Code-coverage Line coverage Functional coverage

Formal Verification:

Equivalence checkers RTL versus Gate Pre-layout versus post-layout Net list Assertion based property checkers(Mathematical techniques to allow larger state space coverage)

Timing Verification:

With whom the Chip is talking to (To know the Interface Timing's) What is the Timing-budgets with in the chip, and how to constrain it within each I.P. and finally analyzing and signing for Timing-targets How to address the timing targets with varying process parameters(on-chip variation) what is the optimal de-rating number to be set so that variations are addressed. Steps to minimize the clock-jitter.

Physical Verification:

Is my design manufacturing process friendly ?

DRC (Design Rule Check) LVS Antenna Checks ERC ESD checks

Noise Simulation:

How Noisy is my design so need to perform noise simulations addressing these areas

Simultaneous Switching Noise (SSN) Package Noise EMI Noise Power-ground noise Cross-talk noise Analog Noise Substrate noise Power Simulations:

When a digital logic gate switches, it pulls a surge of current through the power and ground pins connected to it. The inductance of those pins (and their bond wires) converts that surge to an internal drop in supply voltage and rise in ground voltage on-chip (relative to a PCB ground plane). Those voltage fluctuations may not be enough to interfere with digital logic, but they can seriously interfere with the performance of analog circuits. There are several "tricks" to reduce the electromagnetic interference (EMI) of these surges.[6]

  • An independent set of "I/O" power supply pins that is only connected to the output drivers on the I/O pads, separate from the "core" power supply pins that power internal digital logic. This helps prevent switching noise in a processor core from leaking out through the output pins, radiating off PCB traces like an antenna, and interfering with radio and television (and failing FCC testing).
  • An independent set of "analog" power supply pins that power the on-chip analog components (ADC, DAC, etc.) and analog output pads, separate from the "digital" power supply pins. This helps prevent switching noise in a processor core from interfering with the analog components.
  • I/O bus pins (address and data) that only toggle on I/O bus cycles, independent from memory bus pins. A single common bus for all external memory and I/O devices forces each memory access to toggle address and data lines all over the PCB connected to every I/O device, radiating much more noise.
  • spread spectrum clock
  • internal clock doubler or more general clock PLL -- this allows internal processor core to run at a high clock rate, without that high frequency being directly connected to any PCB traces.
  • Put some internal memory on-chip; clock only internal memory (cache RAM or flash memory) at high speeds; use a slower pace to read and write external memory devices.
  • Drive output pins with slower rise and fall times to reduce radiated EMI (even though the pins still have the same number of transitions/second); tolerate slower rise and fall times on input pins.
  • Prefer differential communication buses -- FireWire, USB, XDR DRAM, low-voltage differential signaling, etc. -- rather than inherently noisier single-ended buses -- RS-232, IEEE 1284, the ISA bus, etc.

Is my design meeting power-targets

IR drop analysis Dynamic power simulations

Power related methodologies

Optimum location for De-caps Multiple Voltage domains Multi Vt design DVFS (Dynamic Voltage and Frequency scaling) Clock-gating Techniques Power Management Unit (to shut-off when not required) Level-Shifters across cross-voltage domains

Thermal Simulations

Study the thermal targets and mechanism to reduce thermal problems.

The largest and most obvious thermal problem is permanent failure caused by overheating. One way to avoid that is ...

There are also more subtle problems, such as thermal gradients causing nonlinearity in analog chips. Computer simulations often leave out such subtle effects, creating a "simulations never fail" problem when the actual chip performs much worse than the simulations. Mask Designers carefully lay out amplifiers, placing critical components with symmetry and common-centroid layouts, in order to reject thermal gradients.[7]

Test Simulations

Is my design testable once chip comes out, methodologies to identify the problematic areas

Boundary Scan Memory BIST simulations Tester specific vector generation and simulations Tester vector compression techniques to reduce tester time At-speed testing mechanism's Scan-shift and scan-capture methodologies IDDQ testing Wafer Level Burn-in Tests to know Known Good Dies(KGD) Wire pull tests DC parameter tests AC parameter tests Path-delay tests Delay tests Transition fault testing

Addressing DSM and Yield Issues

Redundant via's Spacing non critical areas to be lithography friendly Wire widening Metal Filling Metal Slotting


Emulates the functional behavior of the design. Synthesizable assertions are mapped to emulators to perform at system speeds.

Hardware prototype:

Prototyping the system requirements in a programmable FPGA's

In spite of all the Verification Methodologies and Strategies if things goes wrong, how to address that in the design - Methodologies to reduce cost & time

Spare-gates Redundant rows/columns in the memories Redundant vias Built-in self repair memories Focused Ion Beam Methodologies

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