File:1st order type 0 slave CDR architecture.png
Size of this preview: 800 × 345 pixels. Other resolutions: 320 × 138 pixels | 901 × 389 pixels.
Original file (901 × 389 pixels, file size: 25 KB, MIME type: image/png)
 |
This is a file from the Wikimedia Commons |
Summary
| Description |
English: Architecture of the simplest CDR. Just a didactical figure.
Presents the case of the slave CDR with a phase controlled VCO. Meant to replace: CDR architectures type 0 first order.png previously uploaded into Wibooks space. |
| Date | |
| Source | Own work |
| Author | BORGATO Pierandrea |
Licensing
I, the copyright holder of this work, hereby publish it under the following license:
This file is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported license.
- You are free:
- to share – to copy, distribute and transmit the work
- to remix – to adapt the work
- Under the following conditions:
- attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- share alike – If you remix, transform, or build upon the material, you must distribute your contributions under the same or compatible license as the original.
File history
Click on a date/time to view the file as it appeared at that time.
| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 14:41, 30 January 2012 | | 901 × 389 (25 KB) | BORGATO Pierandrea | Addition of a finite frequency pole in the intermediate block. Without it, the loop was of order 0! |
| 14:38, 30 January 2012 |  | 901 × 389 (25 KB) | BORGATO Pierandrea | The previous version was incorrect, because the flat gain block made up a type 0, zero order loop. A finite frequency is needed for a type 1 loop, like in the new version. | |
| 10:29, 29 January 2012 |  | 922 × 399 (23 KB) | BORGATO Pierandrea |
File usage
The following page uses this file:
