Wikibooks

VHDL for FPGA Design/State-Machine Design Example Serial Parity Generator

< VHDL for FPGA Design
VHDL for FPGA Design

Serial Parity Generator edit

 

State Diagram edit

 

Simulation Waveform edit

 

Retrieved from "https://en.wikibooks.org/w/index.php?title=VHDL_for_FPGA_Design/State-Machine_Design_Example_Serial_Parity_Generator&oldid=1690896"