VHDL for FPGA Design/Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Decoder is
   port
   (
      Out_Sel : in std_logic_vector(2 downto 0);
 
      y : out std_logic_vector(7 downto 0)
   );
end entity Decoder;
 
architecture Behavioral of Decoder is
begin
   y <= "00000001" when Out_Sel="000" else
        "00000010" when Out_Sel="001" else
        "00000100" when Out_Sel="010" else
        "00001000" when Out_Sel="011" else
        "00010000" when Out_Sel="100" else
        "00100000" when Out_Sel="101" else
        "01000000" when Out_Sel="110" else
        "10000000" when Out_Sel="111";
 
end architecture Behavioral;