Programmable Logic/Verilog Control Structures
Verilog has a number of high-level control structures that can be used to perform complicted tasks with some level of abstraction. These control structures should be familiar to people who have experience programming in high-level computer software languages, such as C or Java.
It is important to note that not all constructs in verilog are compatible with these high-level control structures. Wires and continuous assignments are not generally compatible with these structures, and trying to combine them may either lead to compiler errors or synthesis errors.
IF structures test a particular condition, and execute the following code statement if that condition is true. Following an IF block can be an optional ELSE block, that will be executed if the condition is not true.
IF-ELSE structures can be expanded to account for more than two possibilities by nesting. The pseudocode example below demonstrates this:
if (<condition 1>) <statement 1> else if(<condition 2>) <statement 2> else if(<condition 3>) <statement 3> ... else <statement n>
It is worth noting that additional resources will be generated to handle conditions that aren't accounted for in the IF-ELSE chain. This means that it is typically more efficient to account for all possibilities than to ignore some.
A WHILE loop executes repeatedly, so long as the condition is true. The condition is tested before each execution of the loop.
SWITCH-CASE structures are similar to nested IF-ELSE structures, except they tend to reduce to more efficient hardware structures.
Code blocks are designated through use of the keywords begin and end. Code blocks can be put anywhere that a single statement is valid, but where more than one statement needs to be executed.
Code blocks can be nested.
Variables declared in a code block are lexically scoped to that block.
Naming and leaving Code Blocks
Above described blocks of code can be named, like
begin : somename <statement 1> .... <statement n> end
In combination with the prior described loop constructs, a superior equivalence of Verilog to the break command in C is disable, which receives the name of the block to leave as an argument:
while(1) begin : infiniteLoop <... statements ...> if (somecondition) disable infiniteLoop; <... statements ...> end
In testbeds, one may also decide to use $finish or $stop to break from an execution.Last modified on 7 September 2012, at 20:20