In microprocessor-based software systems, instructions are performed sequentially. Each instruction is allowed to complete before the following instruction may begin. Even in situations where this is not strictly the case, such as pipelined and superscalar processors, the changes to this pattern are transparent to the programmer and can essentially be ignored.
In programmable logic, however, this is the case. Instructions can neither be expected to occur in a particular timeframe, nor in a particular order. Verilog and VHDL both contain constructs to force certain synchonization, although these constructs may carry with them a performance penalty.
Typically, a hardware design should have a clock signal that all the various modules have access to. Actions that occur in response to the clock signal are known as synchronous, and actions that occur without the clock signal are known as asynchronous. Furthermore, through the use of clock multipliers, different modules in a design can be moving at different speeds. Needless to say, timing and synchronization can be very important problems to solve for a hardware designer.