This page is going to discuss the history and development of HDL methods, and the 3 HDL languages that we are going to study in this book: Verilog, VHDL, and SystemC.
History of HDLEdit
Hardware Description Languages (HDL) are programming languages that are designed to program FPGAs and CPLDs. HDL compilers will often create a "gate map" instead of a computer executable file. This gate map can be downloaded onto the programmable device, and run.
There are three common HDLs: Verilog, VHDL, and SystemC. Of these, SystemC is the newest and least popular, although its use has been rising in the industry.
History of VerilogEdit
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC itself stands for "Very High Speed Integrated Circuit").
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
Subsequently, a new working group was formed, IEEE P1800, to build on the IEEE 1364 language along with additional contributions from Accellera. In mid 2004 the IEEE 1364 committee was disbanded, and maintenence on the standard was taken up by the IEEE 1800 working group.
History of VHDLEdit
VHDL stands for "Very High Speed Integrated Circuit (VHSIC) Hardware Description Language", and is a common HDL for use in programmable gate arrays and application specific integrated circuits (ASIC). VHDL is very similar in form to Ada. VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was developed.
The first publicly available version of VHDL, version 7.2, was released in 1985. In 1986, the Institute of Electrical and Electronics Engineers, Inc. (IEEE) was presented with a proposal to standardize the language, which it did in 1987 after substantial enhancements and modifications were made by a team of commercial, government and academic representatives. The resulting standard, IEEE 1076-1987, is the basis for virtually every simulation and synthesis product sold today. An enhanced and updated version of the language, IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been responding by adding these new language features to their products.
Though IEEE Standard 1076 defines the complete VHDL language, there are aspects of the language that made it difficult to write completely portable design descriptions across different vendor tools. The problem stemed from the fact that basic VHDL supported many abstract data types, but it did not address the simple problem of characterizing different signal strengths or commonly used simulation conditions such as unknowns and high-impedance. Simulator companies began enhancing VHDL with new, non-standard types to allow their customers to accurately simulate complex electronic circuits. This caused problems because design descriptions entered into one simulator were often incompatible with other simulation environments. VHDL was quickly becoming a nonstandard. To get around the problem of nonstandard data types, another standard was developed by an IEEE committee. This standard, numbered 1164, defines a standard package (a VHDL feature that allows commonly used declarations to be collected into an external library) containing definitions for a standard nine-valued data type. This standard data type is called std_logic, and the IEEE 1164 package is often referred to as the Standard Logic package.
The IEEE 1076-1987 and IEEE 1164 standards together form the complete VHDL standard in widest use today. IEEE 1076-1993 is slowly working its way into the VHDL mainstream, but it does not add significant new features for synthesis users.
Standard 1076.3 (often called the Numeric Standard or Synthesis Standard) defines standard packages and interpretations for VHDL data types as they relate to actual hardware. This standard, which was released at the end of 1995, is intended to replace the many custom (nonstandard) packages that vendors of synthesis tools have created and distributed with their products.
IEEE Standard 1076.3 does for synthesis users what IEEE 1164 did for simulation users i.e. increase the power of Standard 1076, while at the same time ensuring compatibility between different vendors’ tools. The 1076.3 standard includes, among other things the annotation of timing information to a simulation model is an important aspect of accurate digital simulation. The VHDL 1076 standard describes a variety of language features that can be used for timing annotation. However, it does not describe a standard method for expressing timing data outside of the timing model itself.