File:Delay locked loop, 0th order type 0 and 1st order type 1.png
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Summary
| Description |
English: The delay locked loop is a variable delay line whose delay is locked to the duration of the period of a reference clock.
Depending on the signal processing element in the loop (a flat amplifier or an integrator), the DLL loop can be of 0th order type 0 or of 1st order type 1. |
| Date | |
| Source | Own work |
| Author | BORGATO Pierandrea |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 14:18, 4 February 2012 | | 935 × 596 (72 KB) | BORGATO Pierandrea |
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