File:1st order type 1 loop.pdf
Size of this JPG preview of this PDF file: 799 × 384 pixels. Other resolutions: 320 × 154 pixels | 640 × 308 pixels | 1,024 × 492 pixels | 1,754 × 843 pixels.
Original file (1,754 × 843 pixels, file size: 45 KB, MIME type: application/pdf)
 |
This is a file from the Wikimedia Commons |
Summary
| Description |
English: 3 examples of block diagrams of 1st order type 1 Phase-locked loops intended for use inside CDR circuits.
The equation of each block is present. |
| Date | |
| Source | Own work |
| Author | BORGATO Pierandrea |
This figure is meant to replace an older one, uploaded in 2009 into the Wikibooks site (CDR_architecture_or1_ty1_uf_nofilt.png ). It corrects a minor mistake, offers one more example, and is more consistent with the other figures in the Wikibook "Clock and data recovery".
Licensing
I, the copyright holder of this work, hereby publish it under the following license:
This file is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported license.
- You are free:
- to share – to copy, distribute and transmit the work
- to remix – to adapt the work
- Under the following conditions:
- attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
- share alike – If you remix, transform, or build upon the material, you must distribute your contributions under the same or compatible license as the original.
File history
Click on a date/time to view the file as it appeared at that time.
| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 20:22, 5 November 2011 |  | 1,754 × 843 (45 KB) | BORGATO Pierandrea |
File usage
The following page uses this file: