The jitter tolerance of an equipment Edit
In digital networks it is established practice (see for instance some of the ITU-T Recommendations G7xx ) to specify (e.g. , ), and to characterise by measurement , the jitter that can be tolerated at the input ports of an equipment.
At any frequency of interest, a sinusoidal input jitter is added to the phase of an otherwise flawless incoming signal, and the jitter amplitude is increased as much as the equipment can tolerate. Beyond that limit, the received data stream is not regenerated perfectly and error bits and possibly also slips begin to appear. The same procedure is repeated at different jitter frequencies, to cover all the frequency band of interest for the jitter tolerance and the results are interpolated to obtain a continuous curve.
The boundary of the area (in the plane of jitter frequencies and magnitudes) where the CDR operates without bit errors is then called the curve of jitter tolerance of that equipment.
The errors can either be generated by sampling the received pulses too far from the optimum point, or by slips. In both cases, the tolerance limit has been exceeded.
- Slips can either come from exceeding the range of the phase comparator, or by exceeding the range of an elastic buffer. The slip is a catastrophic event in terms of BER because, after its occurrence, 50% (statistically) of the regenerated bits are seen as errors and 50% (statistically) are seen as fictitiously correct. The BER is as high as it can ever be (until the framing circuits are able to get in sync again).
- Error-ed bits. The CDR under test extracts the clock directly from the pulses of the received signal, and then uses it to regenerate the pulses received. The tolerance limit will be reached when the clock that samples the incoming pulses is too far (too early or too late) from the optimum point (the point of “maximum eye opening”, that approximately coincides with the central point between transitions). Such distance from the central sampling point, beyond which errors begin to occur, is called lateral eye opening ΦLEO. Error-ed bits will give evidence that the tolerance limit has been exceeded (even if they only pop up sparsely in small bursts at the moments of peak amplitude of the periodic phase error that is induced by the jitter sinusoidal oscillation).
- The jitter tolerance curve always has a "low-pass" shape. The tracking ability of an equipment is best at low frequencies and is low at high frequencies.
- At high frequencies, where no more tracking takes place, the equipment can only tolerate the jitter that does not bring the sampling instant to the eye corners. With zero jitter, the sampling point is offset from the central point by the steady state error, if the steady state error is non zero. If the steady state error is zero, the sampling point is in the eye center.
The tolerance at high frequencies is just a horizontal asymptote, and the asymptote value indicates, for the equipment port under measurement, the difference:
ΦLEO - steady state error
- where the steady state error is the possible error corresponding to an offset of the frequency of the incoming pulses from the free-running frequency of the local oscillator.
- Such error is [rad] in a slave system of type 1, and is 0 [rad] in a phase aligner system or in any type 2 system.
- Towards lower frequencies the measured tolerance curve also is asymptotic, but the slope of the asymptote depends on the PLL architecture:
- 0 dB/decade, i.e. horizontal, This indicated that an elastic buffer is present to absorb some large low frequency jitter. The horizontal asymptote indicates that the jitter compensation is finite. (The length of the buffer is approximately twice the magnitude of the tolerance represented by the horizontal asymptote).
- - 20 dB/decade. This indicated that the receiver is a slave (the local oscillator can follow an infinite phase accumulation, as long as its frequency can track the incoming pulse frequency). The - 20 dB/decade slope tells that the PLL is a type 1 loop (or a type 2 loop whose tolerance is "slew-rate" limited).
- - 40 dB/decade. This indicated that the receiver is a slave (the local oscillator can follow an infinite phase accumulation, as long as its frequency can track the incoming pulse frequency). The - 40 dB/decade slope tells that the PLL is a type 2 loop.
- The tolerance curve sometimes looks like the slope of terraced rice field, with more than one flat section after the first left slope. This indicates that more than one CDR is present along the regeneration path between the injection of the test signal, and that some of them operate at different bit rates.
- In general:
- a flat section, or a flat asymptote, indicates that the tolerance is exceeded in a elastic buffer. Note that the lateral eye opening at high frequencies acts as a elastic buffer;
- a section with a slope of -20 dB/decade indicates that (in the related frequency range) the tolerance is exceeded in a PLL operating there like a 1-1 architecture;
- a section with a slope of - 40 dB/decade indicates that (in the related frequency range) the tolerance is exceeded in a PLL operating there like a 2-2 architecture.
The tolerance function, a simulation of the tolerance curveEdit
In a feedback loop, like in a PLL for CDR use, the operation is linear, and the linear modeling remains valid, as long as all blocks in the loop operate within their linearity range.
Increasing the input signal amplitude, a point will be reached where one block reaches the limit of its range of linear operation.
Increasing further the input signal amplitude, the linear model loses its adherence to the real system and the actual operation deviates from the modeled behavior.
When investigating the effects of the timing variation of the input signal (the input jitter), the tolerance function (that can be derived using the border between linear operation and the most important hard non-linearities - see below) is of particular interest. It corresponds to the important characteristic of the CDR that is often a precise requirement, specified and measured as a function of the magnitude of the input sinusoidal jitter at different frequencies. The mathematical function can be very close to the measured curve, and is therefore a fundamental engineering tool.
Reaching with the signal level the onset on hard non-linearity inside an internal block often corresponds to the appearance of errored bits in the regenerated data stream. The input signal has then exceeded the level of the CDR tolerance (such level is a function of the frequency of the input signal).
A mathematical derivation of such jitter tolerance function can be made finding out:
- the block in the loop that is first to reach its limit of non-linear operation and to generate errored bits or slips;
- the amplitude of the (phase) signal inside such block that reaches the limit of linear operation (such amplitude is a function of ω)
- the input signal amplitude (function of ω) that generates such internal signal amplitude.
In mathematical terms, defining as W(jω) the signal at a generic node of the CDR model, and as ± Φtol the deviation tolerated at that node,
the tolerance function is the locus, for every angular frequency ω, of the magnitude of the input signal X(jω) that produces a W(jω) that reaches, at one or both of its sinusoidal peaks, the tolerance level for that node:
is exactly the input (to the CDR) needed for the internal signal to touch the tolerance limit at least at its positive or negative sinusoidal peaks.
Different circuit shortcomings may identify different tolerance functions. These are then combined into one considering, at every frequency, the lowest value among their values.
The function so obtained is called the jitter tolerance function.
In order to derive a tolerance function that simulates well the tolerance curve obtained by measurement, there are 3 (three) fundamental shortcomings of the linear model must be considered :
- the pulse regeneration (= the eye corners and the steady state sampling offset)
- the limited frequency range of the VCO
- the limited range of the (possible) elastic buffer.
The limited range of the phase comparatorEdit
The border of normal operation of a phase comparator is reached when the distance in phase between its two inputs exceeds a certain value.
It does not depend on the absolute value of either input, but on their difference only.
The phase comparator is built so that its range covers without discontinuity the period T of one line pulse, and the PLL is designed so that zero difference between the comparator inputs corresponds to the perfect lock of the loop:
When Φmax is exceeded by the error signal x(t)-y(t), the phase comparator output falls into the next period of its characteristic and its output indicates to the PLL that the closest locking point is now the center of the nearby pulse.
If the transient is short enough the loop has no time to react, the error signal comes back quickly within range, and the output goes back to the original segment of the comparator characteristic. A large burst of errors have affected the CDR, but at the end there is no slip of the recovered clock
If instead the transient lasts long enough for the loop to react, then lock will be achieved at the center of the new segment of the comparator characteristic: a slip has occurred.
Mathematically such limit of linearity of the phase comparator characteristic defines one of the tolerance curves of the closed loop. Such tolerance can be modeled as the locus -for every frequency- of the magnitudes of sinusoidal input signals X(jω) such that :
But, in the particular case of the measurement of the tolerance curve, as well as in the derivation of the tolerance function, the range extremes of the phase comparator are never reached!
Its range may be exceeded during real operation, in particular during the early phase of a difficult acquisition of phase lock, but it will not be reached while finding the tolerance limit.
In fact, the range of error-less sampling corresponds a sub-range of the phase comparator range. Sampling errors do appear as a consequence of sinusoidal jitter when the lateral eye margin is reached, while the comparator range limit is always larger. The following figure helps identify the quantities involved and clarify the related concepts, and the following sub-paragraph addresses the loop tolerance associated with the sampling phase margin.
The pulse regeneration (= the eye corners and the steady state sampling offset)Edit
The tolerance function due to the lateral closure of the eye diagram can be modeled by an equation like the one resulting from the comparator range, but using a tighter range limit, and taking also into consideration the possible sampling offset that exists in some cases.
The input jitter that is not tracked by the PLL leaves a residual (sinusoidal) error between input (that represents the eye center) and output (that represents the sampling instant).
Overall, the output y(t) is not able to track exactly the input x(t) because of two shortcomings:
- a d.c. offset (the steady state error) and
- its (sinusoidal) phase variation is not able to replicate exactly the input (sinusoidal) phase variation, and a (sinusoidal) error of the same frequency remains.
When the sinusoidal error adds to the steady state error the sampling may take place before the beginning transition or after the end transition of the pulse.
Just one, or a few, or a high density of errors are equally relevant in the identification of the tolerance limit. In other words, the limit is meant to have been reached when the sampling takes place in what could be a wrong instant, even if the irregular jitter of the beginning or of the end of the pulse do not necessary imply an error at every bit time, but with a lower frequency of occurrence. (It should be remarked that the "irregular jitter" of the transitions happens at random -due to line noise and I.I.- but to a large extent faster than the sinusoidal jitter of the tolerance measurement or simulation).
where Φleo ≤ Φmax.
When the error signal instantaneously exceeds Φleo, error bits are generated in the CDR with a certain probability.
When the error signal exceeds Φmax and a slip consolidates, the BER remains very high as long as the framing circuits downstream of the CDR re-align (in a real transmission network) or as long as the sequence recognition circuits of the BER tester re-align (in a tolerance curve test set-up) .
The curves in the figure above can be seen as examples, with the exclusion of the flat asymptote towards low frequencies.
The tolerance due to the lateral eye closure decreases with increasing frequency and flattens out at high frequencies.
The clamping of the curves at low frequencies if present because the circuits described incorporate an elastic buffer (see section here below).
There always exists the possibility that the PLL is not able to follow a rapidly changing phase of its input because the rate of change of the VCO phase (i.e. the VCO instant frequency deviation) is limited.
This may happen either:
- because the PLL, still operating within its linear boundaries, is simply limited by the loop intrinsic low-pass behaviour. In this case to a sinusoidal input jitter corresponds a sinusoidal phase error signal as well as a sinusoidal output jitter.
- or because the PLL non-linear boundary is reached in the characteristic of the VCO, or of a block preceding it in the loop forward chain.
The phase error signal is not a sinusoid like the input phase signal. The output phase signal deviates from the sinusoidal input phase with tracts of lower, constant slope.
In this latter case the PLL is " slew-rate" limited. This can occur both because of the VCO characteristics (the VCO gain falls rapidly at the ends of its useful range) or because of the limited range of its drive signal.
The PLL can track the input phase variations, but it cannot react faster than jumping to the frequency extremes of the VCO useful range (the frequency jump is a linear ramp of the PLL phase: the maximum ramp slope of a circuit is called the slew-rate ) . When the phase of the input signal varies more rapidly than the VCO slew-rate, a phase error appears and it may grow and possibly affect the CDR tolerance.
The VCO centering error shall also be kept into consideration: it appears at the CDR output as a frequency deviation from the free-running value: fp - ffr.
The slew-rate limit can be investigated using a sinusoidal input phase jitter, that is the same input signal used for the tolerance curve of the CDR.
- The tolerance is measured with a sinusoidal input jitter whose frequency sweeps the frequency range of interest and whose amplitude at each frequency is increased until errors appear.
A sinusoidal phase function (of time in the case of jitter) has its maximum rate of variation at the zero crossings, and its maximum rate of variation is the tangent at the points of zero crossing. The slope at the zero crossing is the same of its tangent Aωt, i.e. Aω.
Maximum phase slew-rate = maximum frequency deviation.
The phase slope (= the frequency) that the VCO can generate in response to a constant (high or low) drive signal (originated in the phase detector) depends on:
- the amplitude of the drive signal
- the frequency of the VCO immediately before
- whether the VCO reaches one of its range extremes.
It also depends on the relative frequency of input transitions DT, because the CDR behaves as if the PD gain Gφ was reduced (i.e. multiplied) by DT.
- The open loop gain is defined as G = Gφ Gf GVCO.
If the slew rate is generated by a limitation of the VCO drive signal, the loop will track without phase error as long as:
In general, indicating with Δω the max deviation of the VCO frequency, there is no slewing as long as :
Otherwise said, as long as A ≤ Δω / ω , the tolerance is not reduced by the slew rate; when A ≥ Δω / ω , the phase error due to slewing appears and the tolerance is reduced and its limit may be reached.
Unfortunately the phase error due to slewing is a non-linear function of both A and of ω , and it is not possible to compute it with a closed formula, but only with simulations case by case.
It is convenient to restrict the attention to the onset of slewing because:
- it is a prudent (=conservative) estimation of the tolerance function;
- all CDRs are designed so that slewing never appears for any expected condition of input jitter and run-length.
The onset of slewing takes place at thelocus : A = Δω / ω , that corresponds to a slope of -20dB/dec in a Bode diagram of the jitter tolerance.
The asymptote equation is Tol. = 20log10( ( LEO / ( ωj / Δω )2 )1/2)
The margin between the onset of slewing and the A value that makes the peak of the phase error reach the LEO value (that corresponds to the border of the tolerance region) is lower at smaller ω, and increases somewhat with larger ω. When the output phase jitter becomes triangular, like in the figure above, the actual tolerance gradually flattens out towards the asymptote Tol. = LEO.
Acquisition and tracking examples with evidence of slew rate limitationsEdit
A 2nd order type 2 loop goes into slew rate because of the limited HF gain of the loop filterEdit
When tracking becomes difficult because the loop must operate close to its ability to track, the effort becomes evident by the periodic deviation of the phase comparator output (same period as the input jitter) from its average level. In case of a phase detector, such effort is made evident by a reduction of the bang-bang duty-cycle. Around the zero-crossing of the input jitter sinusoid, the PD output stays constant and indicates the onset of a phase error due to slewing.
- The sinusoidal jitter signal must be considered in conjunction with the steady state error because a type 1 loop compensates all frequency differences and wander with a shift of the bias level of the signal driving the VCO. The slew rate slope of the CDR response is consequently increased in one direction and reduced by the same amount in the other direction. This would be exactly true if the VCO corresponded to its simulation model, but is just approximately true because the actual VCO characteristic is never so neat and simple.
When the jitter frequency is too high for a correct tracking, the slew-rate covers the entire jitter period, and the output jitter becomes a triangular saw-tooth of reduced amplitude.The CDR still tracks well because the steady-state frequency error ωp - ωfr is tracked as well, as can be seen in the asymmetry of the triangular output wave.
The following figure illustrates the above remarks with the phase signals of a typical CDR.
IIn this figure the slew rate is generated by the low gain of the loop filter at frequencies higher than ωz (the frequency of the zero of the loop filter). The output wave from the Phase Detector retains its shape, but attenuated, with a ramp during slewing that compensates any steady-state error.Clock and Data Recovery/Structures and types of CDRs/Applications of the 2nd order type 2 architecture
There is another source of slew- rate in a 2nd order type 2 loop, that is the overall limitation of the VCO frequency range forced either by the saturation of the output of the loop filter at large signals, or by the saturation of the VCO characteristic at the extremes of its frequency range. This second source of slew-rate obviously takes places with much larger Δω and much higher ω. In type 1 loops this latter is the only source of slew-rate (see next example).
A 1st order type 1 loop goes into slew rate only because of the VCO range limitsEdit
- During the first 100 simulation steps (1.78 nsec) there is no input signal.
- LOS is asserted in this interval and the CDR is free-running at its centre frequency ωffr, that is 2000 ppm ( 0.2% ) slower than the nominal link frequency ( i.e. the frequency of the remote transmitter) of 6.28 1010 rad/sec. After 1.78 nsec the PLL lags 0.22 rad behind the transmit clock.
- Then the input signal appears (LOS is dis-asserted) with a "step" of +1.25 rad (useful to mark the beginning of the acquisition phase).
- The input signal is flat in phase for the time being (no jitter yet).
- The phase detector jumps from its intermediate state (that was forced by the LOS signal) to its upper state, signalling that a delay is detected.
- This jump propagates without appreciable delay to the VCO drive signal: the VCO jumps to its maximum possible frequency (DT of the incoming signal is 50%) and its phase (i.e. the CDR output phase) increases linearly with its maximum possible slope.
- The VCO maximum frequency is 7.743 108 rad/sec (=12324 ppm) higher than ωp (6.28e10 rad/sec), but this value must be reduced because the actual DT is < 100% (DT=50%), in order to obtain the maximum possible value of 4.71 108 rad/sec (=7499 ppm), that is the "rising" slew-rate of this CDR in the present conditions.
- In a similar way, the "falling" slew-rate of this CDR is -7.22 108 rad/sec (=-11499 ppm). It is larger because of the offset between ωfr and ωp (2000 ppm, i.e. by 1.257e8 rad/sec).
- The output phase catches up with the input after 4.9 nsec.
- The bang-bang detector, that has been frozen to its upper level during the catch-up transient, starts now its typical pattern of bang-bang frequent jumps.
- It may also be remarked that, as long as the PD follows its typical bang-bang pattern, the distance in phase between input and output (=the error signal) remains very close to zero, and there is no evidence of the steady-state phase error typical of linear systems. In this condition the PD operates very close to its middle point, where its gain is extremely high: the steady stye error of a type 1 system can be computed as the angular frequency offset, divided by the open loop gain. As the gain is almost infinite, the error is almost zero during this interval.
- When 300 simulation steps have elapsed (5.35 nsec), the input signal starts an additional sinusoidal jitter with an angular frequency of 7.5 108 rad/sec and a peak amplitude of 1.20 rad.
- The sinusoidal component of the input jitter starts with its maximum slope (9.0 108 rad/sec) and the slew-rate that the PLL can produce is slightly smaller: as indicated above it is 4.71 108 rad/sec
- The output phase cannot follow the input but follows its maximum slope until the input slows down and it can track it again. This happens 2.46 nsec after the start of the sinusoidal jitter.
- Then the tracking resumes until the falling slope of the input sinusoidal jitter becomes too steep and exceeds the maximum negative slew-rate that is -7.22 108 rad/sec.
- Once there has been tracking at one peak of the input sinusoid, all the subsequent cycles are identical, and the average value of the phase error waveform generates the average drive error at the VCO input that corrects the ωp - ωffr difference.
- During the first 100 simulation steps (1.78 nsec) there is no input signal.
The limited range of the (possible) elastic bufferEdit
In general, a buffer may come in various forms, grouped here below in three categories of decreasing added delay:
- Buffer memories used to store and forward large amounts of bits, like packets of a TCP/IP protocol.
- They are often organised by byte, and are written and read with clocks running at the byte rate.
- The memory is so deep -and the added delay is so large with respect to the bit period- that they easily absorb the timing jitter or the frequency mismatch between the write and the read clocks.
- These buffers could be located inside a single clock domain or at the border of two different domains.
- Elastic buffers between clock domains.
- They are meant to absorb or at least to mitigate the effects of jitter, wander and drifts between the clocks of the two domains.
- Their depth is chosen to absorb the clocks drifts with as rare slips as possible. These elastic buffers are not as deep as a buffer memory but much deeper than a phase adder in a phase aligner (see below).
- As there is no prior knowledge of the drift sign, their end of range triggers a reset to the central point.
- They deal with serial transmissions and are essentially based on shift registers clocked with the incoming clock and read with the local clock.
- Their tolerance is studied using linear phase ramps.
- Phase adders for Phase aligner CDRs.
- Only a clock domain is involved and there are no d.c. drifts between the incoming signal and the local clock.
- They are meant to absorb just the a.c. jitter that has been generated in a relatively short timing loop inside an equipment or in a downstream/upstream loop of an access network.
- Their tolerance is studied with sinusoidal jitter i.e. with Fourier transforms.
- The border of linear operation (= of the tolerance) of a phase adder is typically found when the algebraic sum of the phases of its two inputs reaches the minimum or the maximum value allowed for the output range of the adder.
- It does not depend on the value of either input, even though in practice such limits of tolerance are often reached when one input simply swings too wide.
- The mathematical model shall be:
- where +/- Φmax are the largest values that the adder can process linearly.
- As there is no drift at all, but just alternating jitter, at the end-of-range the adder saturates (as explained below for the delay line implementation).
- The model (of steady state condition), with |I1(jω) + I2(jω)| = 0 for the mid output point, is chosen because it matches the corresponding hypothesis that, if the initial delay was not the mid point, then a transient out-of-range with subsequent re-centering has occurred.
- The phase adder of a PLL is a delay line
- In PLLs the phase adder is implemented in the form of a delay line. The input of the delay line is one input of the adder, while the other input simply controls the amount of delay added to the signal that enters the delay line.
- Such adders can tolerate an added delay between zero and the maximum length of the delay line, Dmax.
If a delay is known in seconds, then it can be be converted into radian
multiplying it by the angular clock frequency: [sec] * [rad * sec-1] = [rad].
- The tolerance limit will be in such cases modeled as:
- When the tolerance extremes are exceeded, the delay lines simply saturates in the sense that it either does not add any delay or that it keeps on adding its maximum delay Dmax. In terms of signal phases, the output remains constant at its minimum or maximum value.
- In the case of a phase phase lock loop incorporating the delay line, this means opening the loop until the input jitter changes its direction of variation. The delay range is frozen while the input jitter waveform insists in the same direction and until it starts getting back. At that moment the lock resumes, but the delay range is now translated towards the average value of the incoming jitter by the amount of the sidetracking.
- This achieves some sort of translation of the delay range towards re-centering around the average value of the input the jitter. It is important to observe that this takes place in a discontinuous mode, because the loop keeps on re-locking into the center of the closest pulse in the delayed waveform presented to its phase comparator. This adds an imprecision of ± π to the positioning of the delay line with respect to the incoming signal, and consequently to the loop jitter tolerance from that moment onwards.
- The granularity of the delay line can be as coarse as about 1/3 of the line pulse period (π/2 - ε in theory), or as fine as fraction of one percent of such period. This granularity adds to the imprecision of the point above to reduce the resulting tolerance.
- To model the phase tolerance curve associated to the delay line in the phase alignerthe following points are considered:
- - Initial conditions. Sufficient re-centerings have occurred in the past, and presently the delay is centered with the inevitable imprecision of ± π
- - A granularity of Φgran characterizes the delay line;
- - total delay that the delay line can adjust is Dmax:
- The tolerance limit imposed by the phase adder to the phase aligner is a fixed amount at all frequencies and is modeled as follows:
The curves in the figure above can be seen as examples of tolerance of phase adders in the flat part at low frequencies.. Such clamping of the curves at low frequencies if present because the tolerance of the elastic buffer (present in the circuits of the figure) is independent from the jitter frequency and only depends on the length of the buffer. The tolerance due to the lateral eye closure further reduces the tolerance at mid and high frequencies and ultimately flattens out at very high frequencies, as seen just above.
- It should be emphasized that the jitter tolerance function is:
- neither a transfer function (its output is not generated with input sinusoids of unit amplitude)
- nor a part of the mathematical model in the strict sense
(because it depends on non-linearities for its definition, although it is computed within the boundary of the circuit linear operation, and
because it may be different for different architectural variants belonging to the same model architecture. See the example of the 1st order type 1 phase aligner that has a different tolerance from the 1st order type 1 slave).
- In the cases where the tolerance function is determined only by the maximum difference acceptable inside the phase comparator, the tolerance limit is a consequence of the one sided eye opening and not of the comparator range (that is larger).
- Exceeding the comparator range (±π) generates slips (= very high BER), but exceeding only the lateral eye opening just generates error bursts that can be rather short. The lateral eye opening is reached always before the comparator range is exceeded: the tolerance function (as well as the tolerance curve!) corresponds to the errors that occur at the eye corners. Phase comparator slips (and associated errors) do occur in a CDR, but beyond the limit of tolerance set by the lateral eye aperture.
- The high frequency jitter tolerance corresponds to the LEO and is visible (and measurable) as the horizontal asymptote at the highest frequencies of jitter. From a certain frequency up:
- the PLL does not track at all,
- the jitter imposed to the input signal moves back and forward the signal transitions (already affected by I.I., noise etc.) and
- the sampling clock does not move.
- The tolerance function, derived from equating the phase error to the eye opening, in such case replicates very well, in magnitude, characteristic asymptotes and corner frequencies the diagram that is obtained with actual measurements.
- Where different phenomena cause each a different region of tolerance for a CDR, then the overall CDR tolerance will correspond to a combination of those tolerance regions.
- ITU-T Rec. G.813 (03/2003) in particular Appendix II
- -G.825-2000.03-The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH): 6.1 Jitter and wander tolerance for STM-N input ports
- Ransom Stephens, “Tektronics Jitter 360° Knowledge Series” from http://www.tek.com/learning/
- Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7, IV. SLOPE OVERLOAD, A. Delta-Sigma Analogy, end of page 6: "...the loop is designed to never slew rate limit on any conforming input signal.". http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf.
- Richard C.Walker article, IV. SLOPE OVERLOAD, B. Expression for Slope Overload, page 7.