A VCO block is present in some (not all) types of CDRs.
The VCO (Voltage Controlled Oscillator) is a circuit that outputs a single frequency signal (some VCOs output a sinusoid, some VCOs output a squarewave) in response to the level of the signal applied to its input; the frequency of its output is proportional to the value of its input signal (the latter is sometimes an analog voltage, sometimes a digital number):
It is convenient to study the PLL in the s or jω domain using the phase as the output variable. The model equation is then:
The VCO shall be made track the frequency of the incoming signal pulses (fp) by the feedback of the PLL in the lock state.
As the free-running frequency characteristic of the VCO, ffr, never exactly coincides with fp, the control signal -while the PLL is tracking the input signal - exhibits an offset from its center value, proportional to the frequency mismatch:
Ed should not be confused with Es (that has been introduced earlier in this book and that will be addressed again in some special cases again further on).
Ed is always present in a PLL and has a non-zero value as in the formula above, no matter what the loop type of the PLL is.
Es instead is non-zero only in type 1 PLLs.
The VCO is very often the most critical block in the CDR, because
- it operates at the frequency of the received line pulses fp (or close to). It uses therefore the fastest circuitry in the PLL, along with the phase comparator.
- the value of ffr must be very precise. Precise component like quartz crystals or trimmed R, C, L must therefore be used inside the VCO (The phase comparator does not require precise components).
- it generates most of the added phase noise that the PLL cannot reject or mitigate.
The block that precedes the VCO, and that drives it, i.e. the amplifier/filter, is less critical in the sense of cost, need of precise components and noise.
As a consequence, it is convenient and correct to model and to simulate the PLL under the simplifying hypothesis that the circuit that drives the VCO matches exactly with its output range the input range of the VCO connectd to it.
Frequency accuracy of the VCO for tight jitter rejection of the PLLEdit
Jitter as well as frequency accuracy are both relative concepts.
They describe the relative mismatch of two quantities (two phases that are functions of time, or two frequencies). The mismatch does not need:
- either of the quantities to be considered the reference for the other;
- a third quantity as independent reference.
Frequency accuracy and acquisition time
The free-running frequency of the VCO (ffr) represents the information available inside the CDR about the expected frequency (fp) of the signal to lock into.
The maximum instantaneous difference |fp – ffr| is a known parameter of the CDR, called accuracy and often expressed in ppm as |fp – ffr| / fp .
This accuracy can also be seen as the maximum drift in a second (in cycles per second) that, at the very start of the acquisition phase of the PLL, is present between the phase of the signal to lock into and the phase of the VCO in its free-running state.
All PLLs have a low pass behaviour with respect to the processing of the input phase signal, and their cut-off frequency is called ωn or ωn2.
It will be shown that it takes a time about 1/ωn (for a first order PLL, and about 2/ωn2 for a second order PLL) for a PLL to react to a step change of the input phase and to recuperate about 70% of the distance from the optimum lock-in condition.
The PLL VCO is normally kept in its free running state as long as an incoming signal is not detected (LOS = Loss Of Signal condition).
When released because the LOS has been de-asserted, its acquisition transient is nothing but the same as a reaction to an abrupt phase change.
The acquisition will take place without slips if the PLL reaction time is (approximately) shorter that the time of half a cycle drift:
Dejittering limit, theoretical and practical
The value of the accuracy |fp – ffr| sets the lower limit for the cut-off frequency of the dejittering that the CDR can perform.
It will also be shown that, in most CDR architectures, the tightening of the dejittering bandwidth increases the offset of the sampling time.
- The jitter cut-off frequency in practice will not be as tight as the theory would allow.
- In those CDRs where tight dejittering is required, the jitter cut-off frequency will be appreciably higher than that limit, to leave margin both for manufacturing tolerances and for fast acquisition times, as well as to keep the sampling time offset reasonably small.
- The jitter cut-off frequency in practice will not be as tight as the theory would allow.
Jitter at lower frequencies than the cut-off will be accepted as clock fluctuations, at higher frequencies will be rejected as effectively as possible.
CDRs with a stringent dejittering requirement (=regenerator CDRs) will make use of VCOs with high ffr accuracy, that are typically based on a controlled crystal or on a precise clock reference followed by circuitry that can change phase or frequency around the center value (like DLLs or variable ratio dividers).
The VCO of the PLL as a frequency demodulatorEdit
When a VCO is part of a PLL, the VCO output coincides with the PLL output.
The VCO input instead is a node whose signal tells exactly the frequency at which the VCO, and therefore the PLL, is operating.
In other words, the PLL can be seen as a frequency demodulator of the signal at its input where the VCO input acts as the frequency demodulator output!
In the following pages, the PLL transfer function (from the instantaneous phase of the PLL input x(s) to the instantaneous phase of the PLL (=of the VCO) output y(s)) will be obtained for different PLLs, combining the individual transfer functions of phase comparator, amplifier/filter and VCOs.
Such transfer function is called the PLL “jitter transfer function”:
The VCO transfer function, when the phase is the output variable, is GVCO/s.
The transfer function of the PLL, from input phase to VCO input is:
If, instead of the PLL input phase x(s), the PLL input frequency xf(s)is considered, x(s) must be replaced by the transform of its derivative xf(s): s x(s) = xf(s) → xf(s) = x(s)/s
Apart from the fixed coefficient GVCO, the "demodulator" transfer function (PLL input frequency to VCO input voltage) is the same as the PLL jitter transfer function (PLL input phase to PLL output phase (= VCO output phase)) !
This conclusion may help later in the book to quicker visualize the PLL behavior in some special cases and conditions.
For instance, all PLLs have phase (=jitter) transfer functions with 0 dB gain from 0 to low frequency and high frequency cut-off.
The very same frequency diagram (just scaled by the value GVCO) will hold good for the inherent frequency demodulator, with the same bandwidth, etc.
Modeling and simulation of the VCOEdit
- with (in)accuracy included
Both in the model equations and in the simulation calculation formulae,
the finite accuracy of the VCO can be taken into account adding an input bias to the (ideal) VCO.
The VCO function is represented as a block with linear relation of its input signal (ranging around 0 volt) with respect to its output frequency (that ranges correspondingly around ffr).
It is more convenient to consider the instantaneous phase of the VCO output as output variable, because the inclusion of a VCO block in a PLL model becomes straightforward.
Phase and frequency are related by a differential operation, as the phase is the integral function of the frequency and the latter is the derivative of the former.
As angular frequencies in preference to period frequencies are used in conjunction with Laplace transforms (s = r +jω), the VCO gain GVCO is expressed in [rad/sec/volt] and the (precisely centered) VCO transfer function is written as (see the figure above):
The drive error Ed, preceded by a minus sign, is the signal addition needed at the VCO input to take into account in the model the lack of accuracy of the VCO itself.
A VCO that is absolutely accurate becomes “inaccurate” by the amount (ωp - ωfr) if a d.c. bias equal to -Ed is added at its input. The saturation outside the range ωmin...ωmax is not taken into account by the model, that is linear. Such non-linearity is incorporated instead in the simulation equations.
If the input signal reaches outside +/- 1 volt (see the purple "Curve for simulation" in the figure above), the (simulated) VCO freezes itself either at ωmin or at ωmax, depending whether the input signal is lower than -1 or greater than +1.
To take into account the VCO accuracy (i.e. the mismatch between ωp and ωfr), the VCO shall be simulated as:
The amplifier/filter output swings between -1 and 1 volt, with 0 volt corresponding to 0 volt at its input.
Clamping completes the computation of the amplifier output signal,
simulating at the same time both the amplifier/filter output limitation and the VCO range limitation.
After clamping this output to +/-1 volt, the -Ed bias is added.
As a result, the simulated VCO runs at ωfr when the filter output is 0 volt, ωmax when the filter output is +1 volt and ωmin when the filter output is -1 volt.
To simulate the conversion of the output frequency (linearly proportional to the VCO input) into the output phase, an integration is made.
The first value is computed as the first VCO input multiplied by the discrete time step of the simulation.
Any subsequent entry is the previous value incremented by the present VCO input multiplied by the discrete time step of the simulation.
To take into account the VCO gain, the result obtained in the previous calculation is multiplied by GVCO and the simulated value of the VCO output is obtained.
The PLL closed loop simulation, in addition to the Ed value, will also show the transient and the final value of the corresponding steady state error Es (if finite).
Different types of VCOsEdit
The Sections above have presented with some detail the classic VCO model (that is a valid model for many VCOs in actual CDRs) and have given suggestions on how to simulate it.
The ring oscillator is an example.
When analyzing existing CDRs, different VCOs may be encountered, and a different simulation or model may be more appropriate:
- bang-bang between two frequencies (simple although somewhat noisy, can be integrated easily inside an IC).
- Fixed free running frequency ffr, followed by a variable ratio divider...(possible if the technology allows a start frequency much higher than ωp). The inherent non linearities of the characteristic can be made smaller if a higher start frequency can be chosen and if the division ratio can be controlled with many close steps.
- A DLL whose output can be sequentially (and circularly) taken from the output of each of its stages by a multiplexer, so that the output phase can be varied indefinitely. The multiplexer could be driven:
- by a A/D conversion of the control signal. The resulting VCO is an oscillator controlled in phase and its model is simply a fixed gain. The gain is equal to the delay line control gain Gdl multiplied by the A/D gain (sec/volt) if the VCO output is measured in seconds, or equal to to Gdl x GA/D multiplied by the ratio: delay_line_length / oscillator_angular_frequency, if the VCO output is measured in radian.
- by an integrator plus A/D ( or by an accumulator if the implementation is digital) and then to the control input of the delay line. This adds a 1/s factor to the VCO model
No oscillator is exempt from noise, and the oscillator noise affects the CDR performances.
The output waveform of an oscillator is never perfect in shape and immobile at its nominal frequency. Its power is not an impulse at ffr, but it is distributed around it and exhibits a sort of "bell" shape.
Noise may in theory affect the amplitude, or the phase, or both, in the waveform produced by the oscillator.
Avoiding non-fundamental discussions, it is always assumed that the amplitude of the output waveform of an oscillator is constant and does not contribute to the oscillator noise.
Just its phase (phase or frequency, which is the same thing) jitters and generates the noisy behavior.
In other words, the oscillator noise that can be measured is made up of phase noise only. . This assumption corresponds to the condition that there is no correlation between the power in the upper and lower side-bands.
It is also generally assumed that phase noise is small and can be treated with linear models. This assumption practically corresponds to the condition that the total jitter corresponding to the phenomena under investigation never exceeds π/10.
When a CDR is left free-running because no received signal is present (LOS Loss Of Signal = 1), then all the VCO phase noise is present at the CDR otput. (This is relevant and may become problematic in regenerators, but is not very relevant in end-points and in phase-aligners).
When the CDR is regularly operating and locked, the VCO frequency shifts and coincides with fp.
It will be shown that, when the CDR is in lock, the VCO phase noise that reaches the CDR output is progressively attenuated from the loop characeristic frequency downwards.
Very close to fp the VCO phase noise that reached the CDR output is attenuated to negligible levels.
How much an oscillator deviates from the ideal behavior is normally described by its Power Spectral Density, PSD.
The PSD is always finite, and peaks at ffr when the oscillator (the VCO) is free-running, or at fp when the VCO is locked.
When a CDR is in lock, the PSD of the VCO, centered around fp, exhibits essentially the same side-bands than when free-running.
The PSD curve looks different if the vertical axis scale is logarithmic (used when the side-bands are important) or if the scale is linear (used when the fundamental frequency of oscillation is more important than the side-bands)
The Power Spectral Density of an oscillator can be measured in dBc/Hz (or in another logarithmic unit, that yields the same curve but translated upwards or downwards) or in W/Hz (linear y-scale).
The horizontal x-axis is linear and centered on the fundamental frequency when PSD is described on both sides of ffr, to avoid asymmetrical representation of the two side-bands.
The phase noise proper L(f) (pronounced “script-ell of f”), is defined (and measured) as one half (= the upper half) of the double-sideband PSD of the oscillator. It is a function of the frequency offset between the frequency of measure and the oscillator center frequency.
It may be noted that the definition does not exactly include the oscillator center frequency (or frequency = 0 of phase noise). Very slow phase noise or wander is at the same time difficult to deal with and of difficult measure. It belongs to a different engineering topic, like a very little frequency offset or like a very selective spectrum analyzer or like a measurement that takes a very long time. As it is of vert little or of no practical use for the engineering of phase noise in oscillators, it is left out.
When expressed in decibels, the units of L(f) are dBc/Hz (dB below the carrier in a 1 Hz bandwidth at a distance f from the center frequency).
The logarithmic y-axis representation is necessary when the oscillator noise is measured.
If only the upper side-band of the oscillator phase noise is described, then also the x-axis is preferably logarithmic.
Modeling of the oscillator noise describes just the upper side-band of the oscillator spectrum (and the preferred scale of the x-axis is also logarithmic).
In most practical cases, the oscillator noise PSD uses the oscillator fundamental frequency as a zero reference, and the difference f-ffr as independent variable.
To avoid unnecessary troubles (mathematical ∞/0 for a model; infinite selectivity and/or dynamic range for a measure), the description does not reach down to zero frequency difference, but gets very close (so that only a minor amount of power, i.e. PSD x frequency interval, is neglected).
The well known model was proposed by Leeson (February 1966).
A fundamental paper is also the one from A. Hajimiri and Thomas H. Lee (1998)
- Analysis of Timing Jitter in CMOS Ring Oscillators, Todd C. Weigandt, Beomsup Kim and Paul R. Gray, Proc. of ISCAS, June 1994, a paper included in Monolithic Phase-locked Loops and Clock Recovery Circuits, Theory and Design, IEEE PRESS, ISBN 0-7803-1149-3
- Analysis, Modeling and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators, Behzad Razavi in Proc. CICC, pp. 323-326, May 1995, a paper included in Monolithic Phase-locked Loops and Clock Recovery Circuits, Theory and Design, IEEE PRESS, ISBN 0-7803-1149-3
- Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7.
- IEEE Std 1139-1999 IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology—Random Instabilities, http://www.umbc.edu/photonics/Menyuk/Phase-Noise/Vig_IEEE_Standard_1139-1999%20.pdf
- Clock (CLK) Jitter and Phase Noise Conversion, MAXIM APPLICATION NOTE 3359, http://http://www.maxim-ic.com/app-notes/index.mvp/id/3359
- A General Theory of Phase Noise in Electrical Oscillators, by Ali Hajimiri and Thomas H. Lee, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 http://www.chic.caltech.edu/Publications/general_full.PDF