Limits of the first order PLLEdit
The PLL of the first order, type 1, in spite of its simplicity, has several good features to represent the best choice in certain applications.
For instance, it is preferred to implement a phase aligner (Definition of phase aligner) because the increases of performance offered by loops of 2^{nd} order cannot give any advantage in this particular application;
it may also be a good choice for a simple slave CDR when the incoming bit stream has a high transition density.
For other (slave) CDR applications, the flat gain block (evident in the figure of the slave loop of 1^{st} order) can be modified and made evolve into a 1^{st} order filter (making the loop become 2^{nd} order).
It should be noted that the two other blocks of the first order loop (the phase comparator and the local clock) are necessarily working at the line pulse speed (that is the highest speed in a CDR).
This makes them more complex technologically and more expensive to modify when an improvement of the loop performances is required.
The added filter block works instead at lower frequencies, and its design is correspondingly more flexible.
The filter block is used to implement the desired values of ω_{n} and ζ in the second order loops.
It is always a good design approach to implement a filter that be linear (at least in its practical behavior). The loop modeling and simulation remain possible in all conditions and are simpler than the modeling and simulation of a nonlinear loop, whose models and simulations do not always exist.
The added filtering action allows to better fit specific requirements of other applications and to add some performances that the 1^{st} order loop lacks:
 the input jitter highfrequency cutoff can be made sharper (from 6 dB/octave to 12 dB/octave), a performance important in regenerators (using the 2  1 loop)
 the steady state error resulting from a frequency difference f_{p}  f_{fr} can be compressed to zero, a performance important when G is widely variable and the VCO has poor centering (using the 2  2 loop)
 the jitter tolerance due to the endofrange of the phase comparator (that in a 1^{st} order type 1 slave PLL increases towards the lower frequencies with a slope of 6 dB/octave ) can be increased and present a steeper slope of 12 dB/octave (using a 2  2 loop )
 the low frequency noise generated by the VCO can be better rejected with a sharper lowfrequency cutoff (from 6 dB/octave to 12 dB/octave), a performance important to use low cost, noisy VCOs (using the 2  2 loop).
It should be remarked however that the four points of possible improvement listed above are not relevant in the case of a phase aligner! This is in fact where the 1  1 loop finds its best fit.
Point by point in the list above, for a phase aligner:
 Dejittering the incoming clock is no use, because the recovered clock is not used after the data regeneration;
 f_{p} exhibits some jitter with respect to f_{fr}, but cannot wander away from it. They both belong to the same clock domain;
 the jitter tolerance is limited horizontally by the halfdepth of the phase adder, that cancels any improvement possible at low frequencies to the boundary of tolerance set by the phase comparator;
 the local clock is the reference, and is conceptually impossible to use f_{p} as a reference to identify its low frequency noise!
From 1^{st} order to 2^{nd} orderEdit
Addition of a filter between comparator and VCOEdit
The first order, type 1 PLL is the simplest and corresponds to the simplest (and least expensive!) implementations of CDRs.
In many other applications (of slave CDRs) it is desirable to improve certain performances of the CDR itself, at the expenses of a little increase of complexity.
The "flat gain block" between phase comparator and VCO (clearly identified in the model of the slave 1^{st} order type 1) acquires a first order structure, becomes "the loop filter" and makes the PLL loop a 2^{nd} order loop.
One pole at frequency ω_{f} and one zero at frequency ω_{z} are added to this central block, whose transfer function becomes:
But not all possible choices of locations for the zero and the pole yield a good PLL for CDR. Some shall be excluded so that just two are left:
 The block can neither be a simple integrator 1/s nor a simple differentiator s.
The PLL would oscillate!  The pole shall always be at a lower frequency than the zero.
If not, the rejection of the input jitter at high frequencies would be reduced to a finite flat attenuation. Worse, the filter block would amplify the frequencies higher than ω_{z} with a 6 dB/octave slope: the PLL would become and behave like a type 0 loop. This is not acceptable for slave CDRs: the steady state error corresponding to a finite f_{p}  f_{fr} difference would be infinite!  Therefore the pole at a lower frequency than the zero, and at least one of them at a finite (neither 0 nor ∞) frequency.
 They cannot be close to each other.
The loop would be a 2^{nd} order in name and cost but it would behave in practice not different and not better than a 1^{st} order loop: a wasted effort!  Either the pole at ω_{f} and the zero at frequency ∞ (the loop in this case is a 2  1 loop), or the pole at frequency 0 and the zero at ω_{z} (the loop in this case is a 2 2 loop).
Were they both at finite, though distant, frequencies, just one would be determinant for the loop behavior (the one closer to ω_{n1} = G ).
 They cannot be close to each other.
The natural frequency ω_{n1} of a first order loop is the same quantity as the open loop gain G.
The natural frequency ω_{nx} is a useful concept also in higher order PLLs.
It represents in fact the corner frequency that the closed loop transfer function (= the jitter transfer function) would have
if all frequency shaping was removed from the loop filter (that would be reduced, in such hypothesis, to just a flat gain G_{f}).

 In a 2  1 loop, the natural frequency ω_{n21} cannot be made much lower than ω_{f}, because, as the next page shows, the loop would be underdamped:

 In a 2  2 loop, the natural frequency ω_{n22} cannot be made much higher than ω_{z}, because, as the relevant page shows, the loop would be underdamped:

 If, for instance, the open loop gain G varies (because of manufacturing variability, or of sensitivity to temperature, supply voltage, .., or because of the non linearity of a circuit block), the "non filtered" frequency ω_{n1} ( = G) may come close to the cutoff frequency of the filter ( = ω_{f} or ω_{z}, depending on the loop type 1 or 2) that, in practical circuits, is much more stable than G.


 In a 2  1 loop this would happen if the gain G increased (or if ω_{f} is pushed too much down to tighten the closed loop bandwidth more than ω_{n1});
 In a 2  2 loop this would happen if the gain G decreased (or if ω_{z} is pushed too much up to widen the closed loop bandwidth more than ω_{n1});


 In both cases (increase of G in 2  1, decrease of G in 2  2), looking at the same dependence from another point of view, the damping ratio decreases:

 For both 2^{nd} order loops, ζ should not go below 0.7 (although the type 2 is a little more robust, as the following pages will show).
Targeted to different applications, 1^{st} and 2^{nd} are very different in practiceEdit
When 1^{st} and 2^{nd} are contrasted (in conditions of same cut off frequency) their differences may not seem so large.
Those differences become more evident if the values of the ratio ω_{n}/ω_{p}, requested for different CDR applications, are considered.
1^{st} becomes clearly preferred when a high ω_{n}/ω_{p} (=a short acquisition) is specified, and 2^{nd} when a small ω_{n2}/ω_{p} (a continuous mode application) is specified.
More precisely, in practice:
 1^{st} order loops are used when ω_{n} needs to be just one or two decades lower than ω_{p} (typical case of burst mode receivers), while
 2^{nd} order loops are used when ω_{n2} must be three or more decades smaller than ω_{p} (typical case of the continuous mode receivers).
Another important consideration exists, that addresses the noise generated inside the CDR and its deterioration of the output clock of the CDR.
The noise generated inside the PLL is rejected and does not affect the CDR output in the range of frequencies at which the PLL accepts the input signal as useful, but it propagates to the output if generated in the frequency range at which the PLL rejects the input noise ( i.e. the input jitter ) !
How the PLL reshapes the spectrum of the noise generated inside its own blocks is shown in a dedicated page: Clock and Data Recovery/Noise is shaped by the PLL structure. 2  2 is shown to perform better than 2  1 in this respect.
The 2^{nd} order type 1 is mostly used in cases where ω_{n2} << ω_{p} and, at the same time, it is important that a "jitter clean" clock is regenerated.
Relative strengths and weaknesses of 2^{nd} type 1 and 2^{nd} type 2Edit
Succintly, the 2  1 is best where the input/output requirements are tight and the circuit blocks have good characteristics.
It filters better than the other two loops the noise present in the input signal.
It requires a VCO with reduced noise at low frequencies and a phase comparator with linear characteristics. It is in fact less able to reject the low frequency noise of the VCO, and its damping ratio decreases when the loop gain increases.
It best fits the continuousmode, regenerator applications in professional Telecom equipment.
The 2  2 instead is a best fit where some compromises can be accepted on jitter transfer and generation, but low cost and high integration correspond to circuit blocks with poor characteristics (= nonlinear, noisy, ..).
It filters more sharply the low frequency noise of the (integrated ≈ noisy ) VCO ; its damping ratio decreases when the loop gain decreases.
Despite the lower appeal of its mathematical linear model, the 22 structure is a very frequent choice for monolythic ICs, especially when the line pulse frequency challenges the highest speed of the elementary components of the technology ^{[1]}.
The phase detector is often a bangbang PFD followed by a charge pump, and the VCO is often a LC monolithic oscillator.
External ReferencesEdit
 ↑ Richard C. Walker (2003). "Designing BangBang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 3445, a chapter appearing in "PhaseLocking in HighPerformance Sytems  From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0471447277. http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf.