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Reference is made to the simulator program available at:
https://docs.google.com/leaf?id=0B0nDPhaxcZiPM2EzN2YwNWItNjljNy00MzRiLTkyODMtMjdjNjlkMDNhMTZi&hl=en_US%7C (a new version is in preparation --BORGATO Pierandrea 14:12, 1 September 2013 (UTC)
Application of the 2-2 architectureEdit
This architecture finds its practical applications where a bang-bang phase detector is used and where the Es must be reduced to a minimum (possibly zero). The strong reduction of the low-frequency noise from the VCO is a further bonus.
It therefore lends itself well to monolithic implementations, and this explains its widespread use.
A bang-bang phase detector is inevitable in monolithic applications at very high line frequencies , and monolithic implies also an on-chip oscillator, that is relatively noisy and relatively inaccurate in ωfr.
On the other hand, the high volume applications of today are correspondingly very cost sensitive, and require that a single silicon chip accommodate the whole CDR, and also much more.
In practice a bang-bang phase detector is always used, and the VCO is a linear monolithic one, either a ring oscillator or a low-Q LC.
Consequently all the monolithic:
- line regenerators,
- slave clocks in Telecom networks
- CDRs of portable electronics
are made with this 2 - 2 architecture.
A long run-length can affect the tolerance margin in sampling the received signal, but this is normally mitigated by the use of a ternary phase detector.
Less evident, but still dangerous in a 2-2 loop, a decrease of the transition density may negatively affect the loop tolerance (clarify if actually dangerous in practical implementations).
The linear model of the previous page can recommend the conditions that must be carefully checked, but only a simulation can produce a quantitative assessment of the performance deterioration.
Single zero filterEdit
The key feature of the 2 - 2 architecture is the very high gain at low frequencies of the loop filter. Such gain decreases with increasing frequencies up to the frequency ωz and then remains asymptotically constant and equal to Gf.
It gives this architecture its ability to squeeze the steady state error to zero, but it can also be the origin of unexpected troubles.
When the phase detector outputs a constant request for higher, of for lower, frequency for a significant number of clock cycles,
a temporary lack of bang-bang around the locking condition occurs while the VCO lags behind a rising or falling input phase.
As this interval grows, the contribution of the low frequency gain of the filter increases, and can reach beyond ant tolerable limit.
This can be simulated making the loop respond to a input phase step or attempt to track a sinewave whose amplitude and frequency exceed the maximum slew-rate of the VCO.
Maximum phase slew-rate = maximum frequency deviation.
It should be remarked that the frequency deviation limits of the VCO are often set by the limitations of the filter output, more than by the intrinsic extremes of the frequency range of the VCO itself.
There always exists the possibility that the VCO is not able to follow the rapidly changing phase of the input.
In that situation, the rate of change of the VCO phase is insufficient. The VCO is "slew-rate" limited.