Clock and Data Recovery/Structures and types of CDRs/Applications of the 2nd order type 2 architecture

Reference is made to the simulator program available at:

https://docs.google.com/leaf?id=0B0nDPhaxcZiPM2EzN2YwNWItNjljNy00MzRiLTkyODMtMjdjNjlkMDNhMTZi&hl=en_US%7C (a new version is in preparation --BORGATO Pierandrea 14:12, 1 September 2013 (UTC)


Application of the 2-2 architectureEdit

This architecture finds its practical applications where a bang-bang phase detector is used and where the Es must be reduced to a minimum (possibly zero). The strong reduction of the low-frequency noise from the VCO is a further bonus.

It therefore lends itself well to monolithic implementations, and this explains its widespread use.

A bang-bang phase detector is inevitable in monolithic applications at very high line frequencies [1], and monolithic implies also an on-chip oscillator, that is relatively noisy and relatively inaccurate in ωfr.

On the other hand, the high volume applications of today are correspondingly very cost sensitive, and require that a single silicon chip accommodate the whole CDR, and also much more.

In practice a bang-bang phase detector is always used, and the VCO is a linear monolithic one, either a ring oscillator or a low-Q LC.


Consequently all the monolithic:

  • line regenerators,
  • slave clocks in Telecom networks
  • CDRs of portable electronics

are made with this 2 - 2 architecture.


A long run-length can affect the tolerance margin in sampling the received signal, but this is normally mitigated by the use of a ternary phase detector.

Less evident, but still dangerous in a 2-2 loop, a decrease of the transition density may negatively affect the loop tolerance (clarify if actually dangerous in practical implementations).


The linear model of the previous page can recommend the conditions that must be carefully checked, but only a simulation can produce a quantitative assessment of the performance deterioration.



Single zero filterEdit

The zero is at angular frequency ωz =1/τz,
ωw = 1/τ is the frequency of gain = 1 = 0 dB . τz = Gf τ .

The key feature of the 2 - 2 architecture is the very high gain at low frequencies of the loop filter. Such gain decreases with increasing frequencies up to the frequency ωz and then remains asymptotically constant and equal to Gf. In practice the value of Gf will be lower than 1 making Gf more of an attenuation than of a gain. In this case, the asymptotic gain is also called β.

In the 1 - 1 architecture the output of a bang-bang binary PD always makes the VCO jump from one end of its control range to the opposite end. This leaves a strong residual in the output phase of the PLL, because only the 1/s slope of the VCO characteristic does filter the sharp and large swings.
The 2 - 2 architecture behaves the same for high frequency jitter as its loop filter does not filter out the high frequency components (higher than ωz) that are coming from the comparator output. The filter passes the high frequency components of the jitter to the VCO with a flat transfer function.
It is the value of the loop filter for high ωz that - although flat up to where parasitic poles at even higher frequencies make themselves felt- is much smaller in a 2 - 2 architecture than the equivalent gain in a 1 - 1 architecture and that makes the tracking jitter proportionally smaller. On the other hand, the high amplification that the filter of the 2 - 2 for frequencies lower than ωz does assist in the acquisition phase and reduces significantly any low frequency jitter.

The (almost) infinite gain at low frequencies gives this architecture its ability to squeeze the steady state error to zero, but it can also be the origin of unexpected troubles.

When the phase detector outputs a constant request for higher, of for lower, frequency for a significant number of clock cycles,

a temporary lack of bang-bang around the locking condition occurs while the VCO lags behind a rising or falling input phase.

As this interval grows, the contribution of the low frequency gain of the filter increases, and can reach beyond ant tolerable limit.

This can be simulated making the loop respond to a input phase step or attempt to track a sinewave whose amplitude and frequency exceed the maximum slew-rate of the VCO.


At the same time, it is fundamental to consider also the time that the loop waits before the next update of the input phase that comes from the next transition of the input signal. When a transition comes as soon as possible, the update time is: tupdate = 1/fp.

When a bit of the same sign follows in the input signal, tupdate at least doubles. In actuality tupdate will be equal to 1/fp multiplied by the run-length.

It is convenient to define a parameter ξ = 2 τz / tupdate. The longer the run length, the more critical the loop response may become [2]. In fact, ξ is called the "stability factor".ξ

Maximum phase slew-rate = maximum frequency deviation.

It should be remarked that the frequency deviation limits of the VCO are often set by the limitations of the filter output, more than by the intrinsic extremes of the frequency range of the VCO itself.

A unit step input generates an output with an initial step as high as the high frequency gain,
and a following ramp, with a slope equal to the high frequency gain times the cut-off frequency.



Slew-rate problemEdit

There always exists the possibility that the VCO is not able to follow the rapidly changing phase of the input.

In that situation, the rate of change of the VCO phase is insufficient. The VCO is "slew-rate" limited.


continued..



Long run-length problemEdit

External ReferencesEdit

  1. Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7. http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf. 
  2. Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7


Last modified on 21 March 2014, at 10:37