Clock and Data Recovery/Introduction
Timing in serial data transmission
To transmit digital information along distances longer than the internal bus of a computer, it is necessary to serialise it encoding together the bit stream and its clock.
The resulting signal, during its journey, is less affected by the noise and by the transfer function of the transmission medium.
The data signal and its clock travel together and experience the very same delay.
At the receiving end, the signal is equalised and the noise filtered out as much as possible. Then the timing information is extracted, and the bit stream regenerated.
The electronic circuits that accomplish these functions inside the data receiver are identified as the Clock and Data Recovery block (= the CDR).
The action of recuperating the clock signal from the received signal is inevitably affected by some deterioration: the square wave extracted is not exactly synchronous with the transmit clock. The timing information, i.e. the clock, is essentially carried by the level transitions of the received signal.
Data and clock, during their travel together, have been affected by the noise and by the intersymbol interference and have acquired:
- some inevitable delay, due to the physical transit time, and to the extraction process,
- some timing inaccuracy (= phase modulation, called jitter)
- some errored bits with a (very) low probability, or –in other words- a bit error rate of very low value (e.g. < 10-19)
The jitter can be kept to a minimum with sophisticated clock extraction circuits, but not eliminated. On the other hand, in the network topology there are always points where signals that had been originated by the same clock and have cumulated different jitters along different transmission paths, must be put together again. To absorb the jitter differences an elastic buffer (i.e. a buffer memory) is used.
- Note: a serialised transmission, with clock and data encoded together, becomes necessary when the bit rate and the wavelength at the bit rate frequency become comparable (when different paths travelled by parallel streams can be different by 25% or more of a wavelength).
- For example: at 1 Gbps the wavelength to refer to is:
- c/(1 GHz) = 3 * 10^8 m/s / 10^9 sec-1 = 30 cm.
- Considering that on PCB the speed is 40% lower than in vacuum, the reference distance is 60% of 30 cm, or about 20 cm. As a result, serial encoded transmission @ 1 Gbps becomes necessary when distance differences amongst parallel paths are 5 cm or more.
- The delay difference amongst different parallel paths causes bits, that have been sent at the same instant on different paths, to be received at different clock cycles of the clock at the receiving end. To put them back in sync, it is necessary to insert redundant bits inside each path, so that a frame sync can be detected. Then buffer memories on each path will be used to put back in sync all the bits of the parallel paths. Interfaces with this structure have been proposed, and are in use in some systems.
- In most practical applications though, the approach of serialising several parallel streams of bits (typically 8), with the multiplication of the clock frequency, has been found to be preferable to the alternative approach of adding the sync structure on each bit stream at the transmit end and to recover that, with use of buffer memories, at the receive end.
CDRs and PLLs
This book deals with CDR (Clock and Data Recovery) circuits, but PLLs (Phase Locked Loops) are the circuit blocks that are analyzed and studied.
These PLLs are the important part of a CDR (= used for the Clock Recovery, CR part of a CDR).
The DR (Data Recovery) part of the CDR is not studied in any depth, and only the PLLs that are fit for the Clock Recovery function are studied here.
PLLs used for other applications, like for instance position detection of mobile objects or identifications of non-modulated signals, are not considered.
In recent years, owing to the explosive growth of mobile phones, a lot of development has been made on PLLs inside frequency synthesizers (they are not CDRs). It may be said that nowadays a very large part of the PLLs implementations are in frequency synthesizers.
What this book is all about
This book intends to provide a good theoretical base for the understanding, the study, the analysis and the design of PLL systems meant for CDR applications.
Two perspectives should be distinguished inside it, for an easier grasp:
- Some CDRs that are essentially linear (as far as CDRs can be linear) are studied. Their mathematical models are analysed in detail keeping in mind the real applications where they are used match exactly the model. They are:
- some CDRs with an additional very hard non-linearity are studied. The widespread (and often inevitable) use of essentially non-linear phase comparators (bang-bang) leads to the use of more tolerant -even if less performing- architectures. (The gain of the bang-bang phase detector is not fixed, but varies with the phase difference at its inputs). Such "robust" architectures are:
- 1. Loops of 1st order and of type 1 (exactly as in 1.1.), for applications of "phase aligners" and of "end points".
- 2. Loops of 2nd order and of type 2 (non-preferred if a linear phase comparator is used), for applications of "regenerators" and of "end points". This last architecture (2.2.) is also analyzed in detail using (no other way) a model based on a "linear" phase comparator, but having as an objective the comprehension of its behavior when incorporating a bang-bang phase detector.
For all the listed cases (1.1., 1.2. and 2.2.):
- the model (functions of the complex variable s or of jω) is provided, so that the operation in "small signal" conditions is studied (jitter transfer, jitter tolerance, noise)
- of each PLL block and
- of the overall system
- a simulator program is provided. It accepts as inputs the loop parameters and the input signal characteristics and provies as output a representation of the "large signal" behavior in those conditions, i.e. of the loop acquisition waveform.
Last modified on 5 April 2013, at 13:45