ST - Store - Opcode 50 - RX format Instruction (32 Bit)
- ST 2,N2
- ST 11,106(8,10)
The specific syntax is
- ST source register,displacement(index register,base register)
Where the displacement, index register and base register values will be determined automatically by the assembler if the USING pseudo-instruction has been used, and the target address label used is within 4096 bytes of the value of some base register.
|RX Instruction (4 bytes)|
|Byte 1||Byte 2||Bytes 3 and 4|
|source register||Target Address|
|(In Hex)||(8 bits)
- The first argument is a source register which value is not affected by the instruction.
- The second argument is the target value location address where the contents of the source register are to be stored into. This consists of a base register, an index register, and a displacement address. The displacement is used as an unsigned offset of 0 to 4095 from the value in the base register, and this displacement is added to the value contained in the base register. If the index register is 0, it is ignored; otherwise, its contents are added to the previous result to obtain the final address.
- The base_register and index_register values are 0 to 15. The offset address is 0 to 4095.
The ST instruction is available on all models of the 360, 370 and z/System.
The ST instruction takes the 32-bit integer value contained in the source register specified by the first argument and stores that value in the memory address specified by the second argument (the target address).
The target address is constructed by taking the value stored in the base register, adding to it the value of the 12-bit offset (called a displacement) address, then adding the value stored in the index register (unless the index register is 0, then its contents are not added) to the base and displacement address, to determine the target address. In the above example of the address 106(8,10), the address value stored in register 10 is added to the displacement address 106 (hexadecimal 6A), then the address value stored in register 8 is added to this to create the target address. Had register 0 been used instead of 8, the value stored in register 0 would not have been used.
The target address must be aligned to a word boundary (i.e. 4 bytes). The Condition Code field in the Program Status Word is not changed.
Exceptions and FaultsEdit
- The target address must be within the range of valid memory or an operation exception occurs.
- The target address must be aligned to a word boundary or an address exception occurs.
- The storage key for the target address must be the same as the current process (or the process must be privileged with a key of zero) or a memory protect violate exception occurs.
- To load an 8-bit byte (character) value from memory, see IC.
- To load one or more 8-bit byte values into a register according to a mask, see ICM
- To load a 16-bit half-word value from memory, see LH.
- To load a 12-bit unsigned value into a register or add up to 4095 to the values in one or two 32-bit registers, see LA.
- To copy a 32-bit word value from one register to another register, see LR.
- To load a 32-bit word value from memory, see L.
- To store an 8-bit byte (character) value in memory, see STC.
- To store one or more 8-bit byte values into memory according to a mask, see STCM
- To store a 16-bit half-word value in memory, see STH.
- To store a 32-bit word value in memory, see ST.
- To load a 20-bit signed value into a 32-bit or 64-bit register from an extended (20-bit) signed memory offset, see LAY.
- To load a 32-bit value into a 64-bit register from an extended (20-bit) signed memory offset, see LGF.
- To copy a 64-bit value from one 64-bit register to another 64-bit register, see LGR.
- To load a 64-bit value into a 64-bit register from memory, see LG.
- To store a 32-bit value from a register to an extended (20-bit) signed memory offset, see STY.
- To store a 64-bit value from a 64-bit register to an address in memory, see STG.
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